Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

This paper presents physics based analytical model for center potential, electric field and subthreshold drain current of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG). The expressions are derived from Poisson's equation in cylindrical co‐ordinate system based on parabolic potential approximation (PPA). The influence of technology parameter variations such as gate length, silicon pillar diameter and oxide thickness on electrical characteristics is studied in detail. Developed analytical model results are validated through the good agreement with simulated data obtained from ATLAS 3D simulator. Copyright © 2016 John Wiley & Sons, Ltd.     

Compact modeling and simulation of nanoscale fully depleted DG-SOI MOSFETS

A two dimensional analytical model for nanoscale fully depleted double gate SOI MOSFET is presented. Green??s function solution technique is adopted to solve the two dimensional Poisson??s equation using Dirichlet??s and Neumann??s boundary conditions at silicon-silicon di-oxide interface. Based on the derived 2D potential distribution, surface potential distributions in the Si film are analytically obtained. The calculated minimum surface potential is used to develop an analytic threshold voltage model. Simulation is done using ATLAS simulator for a 65?nm device and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data and other published results.     

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

Two-dimensional modeling of subthreshold current and subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs

The present paper proposes the surface potential based two-dimensional (2D) analytical models of subthreshold current and subthreshold swing of nanoscale double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The surface potential expression has been directly taken from our previous reported work. The effect of various device parameters on subthreshold current and swing like Ge mole fraction, Si film thickness, gate-length ratio and various combinations of control/screen gate work-functions have been discussed. The validity of the present 2D model is verified by using ATLAS^TM, a 2D device simulator from Silvaco.     

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

The tunnel field-effect transistor (TFET) is an ambipolar device that conducts current with the channel in both accumulation and inversion modes. Analytical expressions for the channel potential and current in a TFET with an n-doped channel when operating in the accumulation and inversion modes are proposed herein. The potential model is derived by solving the two-dimensional (2D) Poisson equation using the superposition principle while considering the charges present in the channel due to electron or hole accumulation along with the depletion charges. An expression for the tunneling current corresponding to the maximum tunneling probability is also derived. The tunneling current is obtained by analytically calculating the minimum tunneling length in a TFET when operating in the accumulation or inversion mode. The results of the proposed potential model is compared with technology computer-aided design (TCAD) simulations for TFET with various dimensions, revealing good agreement. The potential and current in an n-type TFET (nTFET) obtained using the proposed models are also analyzed.

     

A new two-dimensional analytical subthreshold behavior model for submicron Triple Material Gate (TM) GaN MESFET

A new two-dimensional (2D) analytical model for a Triple Material Gate (TM) GaN MESFET has been proposed and modeled to suppress the short channel effects and improve the subthreshold behavior. The analytical model is based on a two-dimensional analysis of the channel potential, threshold voltage and subthreshold swing factor for TM GaN MESFET is developed. The aim of this work is to demonstrate the improved subthreshold electrical performances exhibited by TM GaN MESFET over dual material gate and conventional single material gate MESFET. The results so obtained are verified and validated by the good agreement found with the 2D numerical simulations using the ATLAS device simulation software. The models developed in this paper will be very helpful to understand the device behavior in subthreshold regime for future circuit applications.     

A Gate‐Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

A gate leakage current model for advanced MOSFETs has been developed and implemented into the Hiroshima‐university STARC IGFET Model (HiSIM), the first complete surface‐potential‐based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Computational study of double-gate graphene nano-ribbon transistors

The ballistic performance of graphene nanoribbon (GNR) MOSFETs with different width of armchair GNRs is examined using a real-space quantum simulator based on the Non-equilibrium Green’s Function (NEGF) approach, self-consistently coupled to a 3D Poisson’s equation for electrostatics. GNR MOSFETs show promising device performance, in terms of low subthreshold swing and small drain-induced-barrier-lowing due to their excellent electrostatics and gate control (single monolayer). However, the quantum tunneling effects play an import role in the GNR device performance degradation for wider width GNR MOSFETs due to their reduced bandgap. At 2.2 nm width, the OFF current performance is completely dominated by tunneling currents, making the OFF-state of the device difficult to control.     

A systematic investigation of the integrated effects of gate underlapping,dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of \(\mathrm{SiO}_{2}\) as the gate dielectric. Therefore, a hetero gate dielectric \(\mathrm{SiO}_{2}\) on the drain side and \(\mathrm{HfO}_{2}\) on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.     

Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

We have developed a two-dimensional analytical model for the channel potential, threshold voltage, and drain-to-source current of a symmetric double-halo gate-stacked triple-material double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). The two-dimensional Poisson’s equation is solved to obtain the channel potential. For accurate modeling of the device, fringing capacitance and effective surface charge are considered. The basic drift–diffusion equation is used to model the drain-to-source current. The midchannel potential of the device is used instead of the surface potential in the current modeling, considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. An expression for the pinch-off voltage is derived to model the drain current in the saturation region accurately. Various short-channel effects such as drain-induced barrier lowering, gate leakage, threshold voltage, and roll-off have also been investigated. This structure shows excellent ability to suppress various short-channel effects. The results of the proposed model are validated against data obtained from a commercially available numerical device simulator.     

Two-dimensional subthreshold current model for dual-material gate SOI nMOSFETs with single halo

A two-dimensional (2D) model for the subthreshold current in the dual-material gate (DMG) silicon-on- insulator (SOI) MOSFET with a single halo is presented. The model considers single halo doping in the channel near the source and a dual-material gate to derive the channel potential using the explicit solution of the 2D Poisson’s equation. Together with the conventional drift-diffusion theory, this results in the development of a subthreshold current model for the novel structure. Model verification is carried out using the 2D device simulator ISE. Excellent agreement is obtained between the calculations and the simulated results of the model. __________ Translated from Chinese Journal of Semiconductors, 2008, 29(4): 746–750 [译自 : 半导体学报]     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.