Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

基于降维机理模型的储能电池安全充电在线控制技术

大倍率充电会引起储能电池负极析锂，进一步可能会诱发电池热失控并导致安全事故。而析锂副反应与电池负极电位直接相关，通过模型精确预测负极电位，传输至储能电池管理系统调整充电工况，可以有效抑制负极析锂。因此，本文提出一种基于降维机理SP2D(simplified pseudo two-dimensional, SP2D)模型的储能电池安全充电在线控制技术。首先，对P2D(pseudo two dimensional, P2D)模型中部分偏微分方程进行降维简化，建立SP2D模型。同时采用拆解测量、实验标定、算法拟合和文献参考等方法获取相应的模型参数。其次，使用不同倍率的端电压和负极电位实验数据对模型进行验证，验证结果表明模型在不同倍率恒流工况下精度较高。之后，基于SP2D模型结合比例控制器开展了电池无析锂安全充电的仿真工作，结果表明，电池经过1895s充电即达到截止电压4.3 V，且充电过程中负极电位均处于无析锂安全电位区间。最后，对仿真得到充电策略进行循环验证，结果表明提出的充电方法能够实现电池无析锂安全充电。     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Two-dimensional modeling of subthreshold current and subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs

The present paper proposes the surface potential based two-dimensional (2D) analytical models of subthreshold current and subthreshold swing of nanoscale double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The surface potential expression has been directly taken from our previous reported work. The effect of various device parameters on subthreshold current and swing like Ge mole fraction, Si film thickness, gate-length ratio and various combinations of control/screen gate work-functions have been discussed. The validity of the present 2D model is verified by using ATLAS^TM, a 2D device simulator from Silvaco.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

Numerical study of the thermoelectric power factor in ultra-thin Si nanowires

Low dimensional structures have demonstrated improved thermoelectric (TE) performance because of a drastic reduction in their thermal conductivity, ?? _l . This has been observed for a variety of materials, even for traditionally poor thermoelectrics such as silicon. Other than the reduction in ?? _l , further improvements in the TE figure of merit ZT could potentially originate from the thermoelectric power factor. In this work, we couple the ballistic (Landauer) and diffusive linearized Boltzmann electron transport theory to the atomistic sp³d⁵s*-spin-orbit-coupled tight-binding (TB) electronic structure model. We calculate the room temperature electrical conductivity, Seebeck coefficient, and power factor of narrow 1D Si nanowires (NWs). We describe the numerical formulation of coupling TB to those transport formalisms, the approximations involved, and explain the differences in the conclusions obtained from each model. We investigate the effects of cross section size, transport orientation and confinement orientation, and the influence of the different scattering mechanisms. We show that such methodology can provide robust results for structures including thousands of atoms in the simulation domain and extending to length scales beyond 10?nm, and point towards insightful design directions using the length scale and geometry as a design degree of freedom. We find that the effect of low dimensionality on the thermoelectric power factor of Si NWs can be observed at diameters below ??7?nm, and that quantum confinement and different transport orientations offer the possibility for power factor optimization.     

The surface charging effects in three‐dimensional simulation of the profiles of plasma‐etched nanostructures

Particles and fields represent two major modeling paradigms in pure and applied science at all. Particles typically exist in a spatial domain and they may interact with other particles or with field quantities defined on that domain. A field, on the other hand, defines a set of values on a region of space. In this paper, a methodology and some of the results for three‐dimensional (3D) simulations that includes both field and particle abstractions are presented. In our studies, charging damage to a semiconductor structure during plasma etching is simulated by using 3D level set profile evolution simulator. The surface potential profiles and electric field for the entire feature were generated by solving the Laplace equation using finite elements method. Calculations were performed in the case of simplified model of Ar⁺/CF₄ non‐equilibrium plasma etching of SiO₂. Copyright © 2010 John Wiley & Sons, Ltd.     

Efficient optimization‐oriented design methodology of high‐order 3‐D filters using 2‐D and 3‐D electromagnetic simulators

This paper proposes a computationally highly efficient interface between two‐dimensional (2‐D) and three‐dimensional (3‐D) electromagnetic (EM) simulators for the optimization‐oriented design of high‐order 3‐D filters. In a first step, the novel optimization‐oriented design methodology aligns the 3‐D EM simulator response with the 2‐D EM simulator response of a low‐order 3‐D filter by using an inverse linear space mapping optimization technique. Then, a second mapping performs a calibration with the optimal 2‐D and 3‐D design parameters obtained from the first mapping. The optimization of high‐order filters is carried out using only the efficient 2‐D EM simulator, and the calibration equations directly give the design parameters of the 3‐D filter. The potential and the effectiveness of the proposed optimization‐oriented design methodology are demonstrated through the design of C‐band 3‐D evanescent rectangular waveguide bandpass filters with increasing orders from three to eight. Copyright © 2014 John Wiley & Sons, Ltd.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

A 2‐D surface‐potential‐based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs

In recent times, transistors with heavily doped body have generated much interest because of junctionless channel. In addition, proper threshold voltage regulation requires adjustment of the channel doping, as a result of which most of the compact models become invalid as they consider an intrinsic body. In this paper, a compact surface‐potential‐based threshold voltage model is developed for short channel asymmetric double‐gate metal–oxide–semiconductor field‐effect transistors with heavily/lightly doped channel. The 2‐D surface potential is computed and compared with Technology Computer Aided Design, and a relative error of 2–4 % was obtained. The threshold voltage is solved from 2‐D Poisson's equation using ‘virtual cathode’ method, and a good agreement is observed with the numerical simulations. Also, the model is compared with a reference model and a better result is obtained for heavily doped channel. Copyright © 2014 John Wiley & Sons, Ltd.     

Comparison between line and surface integral formulations of the hybrid mode‐matching/two‐dimensional finite element method

The hybrid mode‐matching/two‐dimensional‐finite‐element (MM/FEM2D) technique has been proposed for the analysis of discontinuities with waveguides of arbitrary cross section; this technique combines the computational efficiency of modal analysis with the versatility and flexibility of the FEM approach. In this paper, we present in detail a surface‐integrals and a line‐integrals formulation of the hybrid MM/FEM2D technique, in case the ‘Standard Formulation’ is used as FEM2D formulation. Such formulations allow computing analytically both the normalization and the coupling integrals. Furthermore, we compare the accuracy obtained by using the line‐integrals and the corresponding surface‐integrals formulation. To these aims we present several numerical results. Copyright © 2004 John Wiley & Sons, Ltd.     

A three‐dimensional Monte Carlo model for the simulation of nanoelectronic devices

We present a three‐dimensional (3D) semi‐classical ensemble Monte Carlo model newly developed to simulate a variety of nanoelectronic devices. The characteristics of the 3D model are compared with the widely used two‐dimensional (2D) models. The advantages of our model, in terms of accuracy in modelling the physics behind the operation of nanodevices, are presented by applying it to T‐branch junctions based on InGaAs/InAlAs heterostructures. Simulation of a T‐branch junction with a Schottky gate terminal is presented, using both 2D and 3D models, demonstrating the necessity of using 3D simulation models to study the physics of complex‐geometry nanostructures. Copyright © 2009 John Wiley & Sons, Ltd.     

基于ANSYS分析的铝电解槽电磁场计算方法

为了探讨求解电解槽电磁场的计算方法,在对实际铝电解槽做出合理假设的基础上。利用ANSYS电磁场有限元法,建立了电解槽三维电磁场有限元模型,计算了槽内电流密度分布;根据槽内电流密度分布,利用耦合法求出了熔体电流产生的磁场;采用标量磁位法计算本槽槽周母线及邻槽母线在本槽产生的磁场,熔体电流产生的磁场与槽周母线产生的磁场相加就得到总的电磁场分布。通过对实际230kA试验槽的电磁场分布计算,计算结果和实测结果比较一致,说明了该计算方法的正确性。     

Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models

The objective of this paper is to investigate stress and strain of a special scale package‐substrate on chip for reliability evaluation or manufacture strategy in deep‐seated situation. A two‐dimensional model with one‐half of cross‐section (2D model) and a three‐dimensional model with one‐fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP‐SOC under the condition of the standard industry thermal cycling temperature −40 to125°C. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright © 2008 John Wiley & Sons, Ltd.     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.     

基于电磁斥力机构的10kV快速真空开关

在合理简化的基础上,利用有限元方法建立了电磁斥力机构场路耦合瞬态动力学特性分析的二维有限元模型.为了验证仿真模型的正确性,建立了简化的实验验证模型,并在不同储能电压下对验证模型的放电电流以及满行程时间进行了实际测量,测量结果验证了仿真模型的正确性.在此基础上,就金属盘、分闸线圈的结构参数以及储能电容的容量对电磁斥力的影响进行了仿真分析,得出了一般性的设计指导原则.另外,为了进一步提高快速开关的分闸速度,提出了在线圈周围加装导磁材料以及利用脉冲成形网络作为其放电回路的方法,利用仿真模型对其效果进行了仿真分析.最后利用12kV-40kA-2500A真空开关管、双向电磁斥力机构以及可倒翻碟簧双稳机构研制了10kV快速真空开关样机,实测其固有分闸时间为0.5ms,满行程时间为1.6ms.     

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Three‐dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire‐length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two‐dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18‐µm CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM‐based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay‐power product improvement and 43% area‐delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd.     

A model for carbon nanotube interconnects

In this paper, a semi‐classical one‐dimensional (1D) electron fluid model is built that is based on a classical two‐dimensional electron fluid theory taking into account electron–electron repulsive forces, which are significant in 1D system. We have used 1D fluid model to characterize the carbon nanotube (CNT) as interconnects, built a transmission line model and studied S‐parameters and group delays. We have also compared S‐parameters and group delays of CNT interconnects with the corresponding parameters of Cu interconnects. The results show that the CNT interconnects exhibit superior performance over the Cu interconnects. The results also suggest using CNT as interconnects for radio frequency (RF)/microwave applications. Copyright © 2009 John Wiley & Sons, Ltd.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

Two dimensional analytical modeling of a high-K gate stack triple-material double gate strained silicon-on-nothing MOSFET with a vertical Gaussian doping

This paper presents the two-dimensional analytical modeling of high-k gate stack Triple material double gatestrained SON MOSFET with a vertical Gaussian-like doping profile. The expression for surface potential has been calculated by solving the 2-D Poisson’s equation and by considering the parabolic potential approximation. The threshold voltages as well as the electric field are also calculated for the proposed model. In addition, detailed studies of the device response towards the various short-channel effects are also examined. The analytical results are verified using the results obtained from a 2-D device simulator, namely ATLAS, Silvaco.