On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.     

Nano Watt CMOS temperature sensor

In this paper, an ultra-low power embedded full CMOS temperature sensor based on sub-threshold MOS operation is designed in a 0.18 μm CMOS technology. It focuses on temperature measurement using the difference between the gate-source voltages of transistors operated in sub-threshold region that is proportional to absolute temperature. By using the proposed scheme the wide range supply voltage of 0.6–2.5 V with inaccuracy of +0.55 °C/V and total power consumption of merely 7 nW at 120 °C is achieved. The performance of the sensor is highly linear and the predicted temperature error is ±2 °C in the range of 10–120 °C. The sensor occupies a small area of 67 × 31 μm². Ultra-low power consumption of the sensor illustrates proper operation for low power applications such as battery powered portable devices, passive RFID tags and wireless sensor network applications.     

Low-Noise Low-Pass Filter for ECG Portable Detection Systems with Digitally Programmable Range

This paper presents the design of an operational transconductance amplifier-C (OTA-C) low-pass filter for a portable Electrocardiogram (ECG) detection system. A fifth-order Butterworth filter using ladder topology is utilized to reduce the effect of component tolerance and to provide a maximally flat response. The proposed filter is based on a novel class AB digitally programmable fully differential OTA circuit. Based on this, PSPICE simulation results for the filter using 0.25-μm technology and operating under ±0.8 V voltage supply are also given. The filter provides a third harmonic distortion (HD3) of 53.5 dB for 100 mV p-p @50 Hz sinusoidal input, input referred noise spectral density of , total power consumption of 30 μW, and a bandwidth of 243 Hz. These results demonstrate the ability of the filter to be used for ECG signal filtering that is located within 150 Hz.     

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

Design and fabrication of 2.4 GHz pre-biased rectifier

A 2.4 GHz rectifier operating in a region of low RF input power was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input signal. Since a rectifier needs an RF signal higher than the threshold voltage of transistors, we introduced a pre-biasing circuit to compensate for the threshold voltage. A low-voltage digital circuit, subthreshold voltage regulator, and low-power level shifter were introduced for reducing the power consumption of the pre-biasing circuit and increasing the driving voltage for the switches at the same time. The circuit simulations revealed that the pre-biasing circuit was effective in a low RF input power region. However, the output voltage was degraded in a high power region. Then, we combined the pre-biased rectifier in parallel with a non-biased rectifier. Three types of rectifiers consisting of LC matching circuits, three-stage rectifier cells, and biasing circuits were designed and fabricated using a 0.18-μm mixed signal/RF CMOS process with one poly and six metal layers. The fabricated pre-biased rectifier operated in a region of RF input power of less than ?15 dBm, while the non-biased rectifier could not operate in this region. The parallel combination of pre-biased and non-biased rectifiers effectively solved the drawback of the pre-biased rectifier in a high RF input power region.     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

A SAR-based ΣΔ modulator using shared DAC

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the ΣΔ modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time ΣΔ modulator is designed and simulated in 0.18 μm CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth.     

Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-V_PP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm² (with PADs).     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.     

一种采用新型延迟模块的上电复位电路

本文设计了一种在低电压下工作的用于射频标签的上电复位电路。此电路一方面采用了一种新型电平检测模块,可以实现精准的电平检测;另一方面采用了一种新型延迟模块,该模块可在0.8V—5V电源电压下工作,可实现100nS到1mS之间的延时;此外,为了降低功耗,电路在产生上电复位信号将利用数字电路产生一个反馈信号来关断整个电路。本文采用smic0.18um的工艺,利用cadence对其功能进行仿真,结果表明该电路可在1.2V工作电压下进行有效复位,并且可以快速的二次复位,复位脉冲宽度为20us左右,功耗极低,完全满足RFID标签的要求。     

射频识别芯片设计中时钟树功耗的优化与实现

UHF RFID是一款超高频射频识别标签芯片,该芯片采用无源供电方式,对于无源标签而言,工作距离是一个非常重要的指标,这个工作距离与芯片灵敏度有关,而灵敏度又要求功耗要低,因此低功耗设计成为RFID芯片研发过程中的主要突破点。在RFID芯片中的功耗主要有模拟射频前端电路,存储器,数字逻辑三部分,而在数字逻辑电路中时钟树上的功耗会占逻辑功耗不小的部分。本文着重从降低数字逻辑时钟树功耗方面阐述了一款基于ISO18000-6Type C协议的UHF RFID标签基带处理器的的优化和实现。     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

A high efficiency transmitter and receiver for magnetic resonant wireless battery charging system in 0.35 μm BCD

This paper presents a transmitter and receiver for magnetic resonant wireless battery charging system. In the receiver, a wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, 1-stage voltage multiplier or 2-stage voltage multiplier mode. As a result, a rectified DC voltage is output from 7.5 to 19 V for an input AC voltage of 5–20 V. In the transmitter, a class-E power amplifier (PA) with an automatic power control loop and load compensation circuit is proposed to improve the power efficiency. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented using 0.35 μm BCD technology with an active area of around 5,000 × 2,500 μm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94 %.The maximum power efficiency of the receiver is about 70 %. The transmitter provides an output power control range of 10–30.2 dBm. The maximum power efficiency of the PA is 71.5 %.     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.     

Pulse amplitude-modulated time-based interface for off-chip interconnect

An increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.