Complexity of a software GSM base station

There is increasing interest in developing radio-based applications in software. The new architecture for implementing mobile telephony base stations has the potential of offering many benefits: great cost savings by using one transceiver per base transceiver station (BTS) instead of one per channel, tremendous flexibility by moving system-specific parameters to the digital part, and allowing the support of a wide range of modulation and coding schemes. A very important problem in designing software radio applications is the need to estimate the required complexity of processing to dimension systems. For example, with a software GSM BTS it is critical to estimate the number of channels that can be supported by a given processor configuration, and to predict the impact of future processor enhancements on its capacity. This article focuses on the design of a software implementation of a GSM BTS and proposes a platform-independent evaluation of its computational requirements based on SPEC benchmarks. It focuses on the design and performance of a library of software modules. Portability and computational requirements are discussed     

Présentation d’une technique 3D d’accélération de la recherche de rayons application aux télécommunications microcellulaires

Development of telecommunications using mobile phones requires the installation of many base stations (BTS) in order to cover the large number of cells which make up the network. Existing systems (GSM, DSC) use carrier frequencies within the microwave range. Ideally, operators should have simulation software to determine the position of BTS. This software would be used initially to determine the geometric configuration of the cells. The next step would be to optimise the radiation pattern of each BTS antenna. In this article we present a method for determining radioelectric coverage based on image theory adapted to the problem, which is more accurate and less time-consuming than conventional methods.     

High-performance DSPs

The processing delay is a serious constraint for speech communication. A one-way end-to-end delay of more than 150 ms can severely degrade the quality of real-time conversations. The components of the total system delay includes the speech frame size, the look ahead, other algorithmic delays, multiplexing delay, processing delay for computation, and transmission delay. At the transcoder rate adaptor unit (TRAU), the only delay that can be manipulated is the processing delay. The TRAUs are generally positioned remote to the base transceiver station (BTS). The channel codec units (CCUs) are located in the BTS. In general, 16 kbit/s traffic channels can be used for full rate speech between the TRAU and BTS. By putting the TRAU remote to the BTS, DSPs for speech coding can be utilized more efficiently to cut system cost. High performance DSPs, such as the Lucent DSP16000, can be used to further cut the cost per speech channel. This article presents an implementation of GSM enhanced full rate (EFR) codec on the Lucent Technologies' DSP16000. The original European Telecommunications Standards Institute (ETSI) C code has been restructured to address the issues of MIPS (million instructions per second), RAM usage, and processing delay. We give a performance overview of vocoder implementations on some existing fixed-point DSPs and discuss the architecture of the DSP16000. Details on how the ETSI C code is restructured are presented. The DSP16210 implementation results are then discussed     

虚拟无线电技术及其应用

近年来软件无线电技术已成为无线电通信领域的技术热点。文中首先介绍软件无线电的基本概念、体系结构及其关键技术 ,在此基础上着重探讨软件无线电的发展新趋势虚拟无线电 (virtualradio)技术 ,通过与传统软件无线电技术的比较 ,分析其优势所在 ,并以SpectrumWare系统为例 ,提出了采用虚拟无线电技术实现GSM收发信基站的软件模块设计方法。     

A Partial CSI Estimation Approach for Downlink FDD massive-MIMO System with Different Base Transceiver Station Topologies

Massive multiple-input multiple-output (massive-MIMO) is a promising technology for next generation wireless communications systems due to its capability to increase the data rate and meet the enormous ongoing data traffic explosion. However, in non-reciprocal channels, such as those encountered in frequency division duplex (FDD) systems, channel state information (CSI) estimation using downlink (DL) training sequence is to date very challenging issue, especially when the channel exhibits a shorter coherence time. In particular, the availability of sufficiently accurate CSI at the base transceiver station (BTS) allows an efficient precoding design in the DL transmission to be achieved, and thus, reliable communication systems can be obtained. In order to achieve the aforementioned objectives, this paper presents a feasible DL training sequence design based on a partial CSI estimation approach for an FDD massive-MIMO system with a shorter coherence time. To this end, a threshold-based approach is proposed for a suitable DL pilot selection by exploring the statistical information of the channel covariance matrix. The mean square error of the proposed design is derived, and the achievable sum rate and bit-error-rate for maximum ratio transmitter and regularized zero forcing precoding is investigated over different BTS topologies with uniform linear array and uniform rectangular array. The results show that a feasible performance in the DL FDD massive-MIMO systems can be achieved even when a large number of antenna elements are deployed by the BTS and a shorter coherence time is considered.

     

A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications

This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and for co-existence with cellular and Bluetooth systems in the same terminal. The direct-conversion transceiver architecture is optimized in each mode for low-power operation without compromising the challenging RF performance targets. A key transceiver requirement is a sensitivity of -77 dBm (at the LNA input) in 54 Mb/s OFDM mode while in the presence of a GSM1900 transmitter interferer. The receiver chain achieves an overall noise figure of 2.8/3.2 dB, consuming 168/185 mW at 2.8 V for the 2.4/5GHz bands, respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70 GHz f/sub T/ 0.25-/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6 mm/sup 2/.     

GSM基站收发信机中的功率放大电路分析

基于爱立信公司的GSM基站收发信机原理,从电路方面对射频放大器进行了匹配分析和稳定性分析,说明了爱立信公司的GSM基站的一些特点.     

ASP modules: cost-effective building-blocks for real-time DSP systems

ASP (Associative String Processor) architecture and support software provide the base technology for the development of versatile, replaceable, and highly compact building-blocks for the simple construction of modular real-time DSP systems, offering step-function improvements in cost-performance, application flexibility, reliability, and ease of maintenance. Based on a fully programmable and fault-tolerant homogeneous computational architecture, emerging from research at Brunel University and being developed by Aspex Microsystems, ASP modules offer cost-effective support of a particularly wide range of DSP applications, by mapping application data structures to a common string representation supporting content-addressing, parallel processing and a reconfigurable inter-processor communication network. Moreover, by exploiting state-of-the-art microelectronics and packaging technologies, the ASP modules achieve processor packing-densities which are more ussually associated with memory components. Indeed, the ASP has been designed to benefit from the inevitable VLSI-to-ULSI-to-WSI technological trend, with a fully integrated simply scalable, and defect/fault-tolerant processor interconnection strategy. The architecture, software, and implementation of ASP modules are discussed, and the paper indicates that the potential of a peak performance of 1 TOPS (i.e., 1E12 operations (e.g., 12-bit adds) per second) with an input-output bandwidth of 3,200 Mbytes/second could be achieved with only 10 ASP modules, within less than a cubic-foot, dissipating 1 KW, and for less than $1M.     

浅析基站隐性故障检测与处理方法

针对基站隐性故障检测难题,研究多种检测手段结合互补,对后台异常性能指标进行分析,筛选出存在隐性故障的小区及定位故障所在设备,借助用雷卡测试仪表进行检测和处理验证,并通过试点案例分析研究出能准确快速定位隐性故障的方法。     

基于GSM900M升级的EDGE＋＋应用及评估

EDGE＋＋的本质是FDD-LTE技术,可以通过升级农村的GSM900M且在共用现网TD-LTE的核心网、PTN传输网基础上改造完成。硬件上,将GSM900M的RRU替换为EDGE＋＋的RRU,BBU侧增加EDGE＋＋的基带处理板和主控板,GSM900M的天馈资源无需替换。软件上,通过Refarming GSM工具清理出农村的空闲频率5M,升级EDGE＋＋的eNodeB的软件版本,修改GSM900M的BTS的相关模式,联调EDGE＋＋的eNodeB,打通EDGE＋＋的eNodeB到EPC之间的PTN传输通道,完成eNodeB站点业务调测。最后,将EDGE＋＋信号通过支持EDGE＋＋的MiFi或CPE终端转换成Wi-Fi信号,在农村提供Wi-Fi热点。     

Low-Complexity Load Balancing with a Self-Organized Intelligent Distributed Antenna System

A high call blocking rate is a consequence of an inefficient utilization of system resources, which is often caused by a load imbalance in the network. Load imbalances are common in wireless networks with a large number of cellular users. This paper investigates a load-balancing scheme for mobile networks that optimizes cellular performance with constraints of physical resource limits and users quality of service demands. In order to efficiently utilize the system resources, an intelligent distributed antenna system (IDAS) fed by a multi base transceiver station (BTS) has the ability to distribute the system resources over a given geographic area. To enable load balancing among distributed antenna modules we dynamically allocate the remote antenna modules to the BTSs using an intelligent algorithm. A self-optimizing network for an IDAS is formulated as an integer based linear constrained optimization problem, which tries to balance the load among the BTSs. A discrete particle swarm optimization (DPSO) algorithm as an evolutionary algorithm is proposed to solve the optimization problem. The computational results of the DPSO algorithm demonstrate optimum performance for small-scale networks and near-optimum performance for large-scale networks. The DPSO algorithm is faster with marginally less complexity than an exhaustive search algorithm.     

LTE/GSM多模基站收发信台数字中频模块故障诊断的新方法

针对LTE/GSM多模基站收发信台（BTS）开发中FPGA数字中频模块故障诊断的需求,开发 了一种基于以太网数据通信接口,利用Matlab软件直接存取FPGA内部寄存器值,并且可以连 续采集数字中频模块内部关键节点大块数据的软硬件协 处理方法,从而快速定位数字中频信号链路的调测问题并帮助排除故障。这种诊断方法无缝 集成在FPGA设计中,可以在BTS测试开发的各个阶段采用,不需要额外设备及接口。在LTE/G SM MSR（Multi-Standard Radio）项目中利用该诊断技术完成了数字中频模块上下行信号 处理链路频谱异常等故障的诊断与定位。     

Development of the Base Station Transceiver Subsystem in the CDMA Mobile System

The base station transceiver subsystem (BTS) of the CDMA Mobile System is interfaced to mobile stations over the air and to the wired network through a packet switched interconnection network. The potential benefits of CDMA technology are achieved when the transmitter and the receiver are properly designed and implemented. The physical layer of the air interface at the base station is implemented with the CDMA ASICs and control circuits in the channel card of the BTS. We present the design perspectives and structural illustration of the BTS. Base station modem ASICs and their control to implement the CDMA receiver, baseband and RF signal processing blocks, and BTS controller are described. Elaborate power control is essential to ensure the high capacity which is one of advantages of the CDMA technology. The closed loop reverse link power control and the forward link power control operated in the BTS are described.     

2G与3G混合组网策略研究

WCDMA技术是3G标准系列家族中三大主流标准之一,能够实现GSM网络的平滑过渡.本文从WCDMA基站和GSM基站之间的互干扰、链路预算以及容量方面分析了WCDMA基站和GSM基站共站的可行性.另一方面,考虑到WCDMA无线网络与GSM的不同及其特点,对混合组网的策略进行研究.     

Effects of rain fading on the efficiency of the Ka-band LMDS system in the Taiwan area

This work presents the effects of rain on the performance of a Ka-band local multipoint distribution system (LMDS) in Taiwan. The rain distribution statistics, from 2-yr measurements with 1-min temporal resolution and 12-yr measurements with a 1-h temporal resolutions, were analyzed. The rain-attenuation model that takes local rain effects is established statistically. These statistical data are used to analyze the performance of the LMDS in terms of its signal-to-interference (S/I) ratio, bit-error rate (BER), and channel capacity at various service distances. From the analysis, it is found that the light rain events induce better S/I for cellular network service, because other base transceiver station (BTS) interference signals around the main BTS are likely to be blocked by rain. The probability that below the nominal value of the channel capacity, when there is rain fading without cellular interference, meets a margin of BER=10/sup -6/ in a 6-km cell using quaternary phase-shift keying (QPSK) modulation. However, when the cellular interference is presented, the effective BTS service distance greatly shrinks to 2-3 km. In summary, in a cellular network environment, as the cell coverage radius is reduced, the effective BTS service range will be correspondingly compressed, suggesting that the cellular interference is even more serious than the rain attenuation itself.     

FPGA prototyping of a RISC processor core for embedded applications

Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain. In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-specific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. We show how hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow. While previously hardware emulation required massive investment in design effort and special purpose emulators, an emulation approach based on high-density field-programmable gate array (FPGA) devices now makes hardware emulation practical and cost effective for embedded processor designs. To reduce development cost and avoid duplication of design effort, FPGA prototypes and ASIC implementations are derived from a common source: We show how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base     

Low-cost and low-electromagnetic-interference packaging of optical transceiver modules

The low-cost and low-electromagnetic-interference (EMI) packaging of optical transceiver modules employing housings of plastic composites are developed and fabricated. Optical transceiver modules fabricated by the plastic composites with transmission rates of 1.25 and 2.5 Gb/s are tested to evaluate the electromagnetic (EM) shielding against emitted radiation from the plastic packaging. The results show that these packaged optical transceiver modules with their high shielding effectiveness (SE) are suitable for use in low-cost and low-EMI Gigabit Ethernet lightwave transmission systems. By comparison of cost, weight, and shielding performance for optical transceiver modules fabricated by the housings of nylon and liquid-crystal polymer with carbon fiber filler composites, woven continuous carbon fiber (WCCF), and nanoscale hollow carbon nanocapulses (HCNCs) epoxy composites, the WCCF composite shows lower cost, lighter weight, and higher EM shielding than the other types of composites. Future studies may develop the low-cost and low-EMI optical transceiver modules using nanoscale HCNCs that have the combination of excellent physical and mechanical properties, light weight, and thinness compared with the conventional fabrication techniques.     

Performance evaluation of multicast relay network using LDPC and convolutional channel codes along-with XOR network coding

In this paper,we have compared the performance of joint network channel coding(JNCC) for multicast relay network using low density parity check(LDPC) codes and Convolutional codes as channel codes while exclusive or(XOR) network coding used at the intermediate relay nodes.Multicast relay transmission is a type of transmission scheme in which two fixed relay nodes contribute in the second hop of end-to-end transmission between base transceiver station(BTS) and a pair of mobile stations.We have considered one way and two way multicast scenarios to evaluate the bit error rate(BER) and throughput performance.It has been shown that when using XOR network coding at the intermediate relay nodes,the same transmission becomes possible in less time slots hence throughput performance can be improved.Moreover we have also discussed two possible scenarios in the proposed system model,in which both diversity and multiplexing gain has been considered.It is worth notifying that BER and throughput achieved for LDPC codes is better than Convolutional codes for all the schemes discussed.     

基于FPGA的GPS＋GSM双重车载定位系统设计

为了克服一般车载导航系统定位不连贯的缺陷,利用NiosⅡ软核处理器配置灵活、扩展性强等特点,结合GPS和GSM模块,设计出了一种基于SoPC技术的双重定位系统。该设计利用SoPC Builder开发工具将NiosⅡ处理器、存储器和接口等组件及μC/OS-Ⅱ操作系统快速地嵌入到FPGA中,用单个芯片完成了人机交互模块、控制模块和通信模块等功能,较一般的GPS导航设备更能实现较高精度的实时连续系统定位,且该设计在不改变硬件的基础上可方便升级、扩展更多功能。     

G729 Voice Decoder Design

Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part—the autocorrelation computation—using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13 Kbit/s, APC 9.6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation.