一种新的失效分析技术——光辐射检测技术

光辐射检测技术是一种新的失效分析技术，它能确定器件失效部位，区分失效机理，还可以进行光谱分析。这项技术可用来研究器件的ＰＮ结退化，寄生晶体管效应，热电子退化、、Ｉ／Ｏ保护电路中的ＥＳＤ技术，介质层漏电和击穿退化等，具有灵敏度高，非接触，非破坏的特点。本文对光辐射检测技术及其在器件失效分析方面的应用情况作了一个全面的介绍。     

叠层高k栅介质中远程界面粗糙散射的理论模型

利用双子带近似,从理论上研究了远程界面粗糙散射对叠层高k栅介质MOSFET反型载流子迁移率的退化作用,模拟了叠层高k栅介质结构参数和材料参数对远程界面粗糙散射的影响。结果表明,对于精确的迁移率模型,远程界面粗糙散射必须加以考虑,另外,在设计叠层高k栅介质MOSFET时,在EOT得到满足的条件下,尽可能利用具有较高介电常数的界面层和具有较低介电常数的高k栅介质,可以减小迁移率退化。     

HfO_2/TaON叠层栅介质Ge pMOSFET制备及迁移率退化研究

为提高high-k/Ge界面质量,在high-k介质和Ge表面引入薄的TaON界面层。相对于没有界面层的样品,HfO2/TaON叠层栅介质Ge pMOSFET样品的空穴迁移率有显著提高,但仍小于理论预测值。利用high-k栅介质MOSFET中各种新的附加散射机制,分析了迁移率退化的原因,模型计算结果与实验结果一致。     

两层旋电磁介质球电磁散射的球矢量波函数解

在均匀旋电磁介质球矢量波函数的基础上,利用球Bessel函数的特性,给出了两层旋电磁介质球内的电磁场用波函数表示的表达式.在平面波入射情况下,应用电磁场在球边界上切向电场和磁场连续与远区辐射条件,导出了两层各向异性旋电磁介质中电磁场用矢量波函数表示的展开函数所满足的方程组,求出了两层旋电磁介质球的散射场用均匀各向同性波函数展开的展开系数,进而得出了两层旋电磁介质球对平面波的电磁散射特性.理论分析和数值计算的结果表明:当两层旋电磁介质球的媒质参数相同时,本文所得的结果可退化为单层各向异性旋电磁体解析解.     

MOS器件栅介质层陷阱的表征方法

随着MOS器件按比例缩小,MOS器件的可靠性问题正成为限制器件性能的一大瓶颈。作为可靠性研究的一个热点和难点,MOS器件栅介质可靠性的研究一直是学术界和工业界研究的重点。普遍认为,栅介质中的陷阱是引起栅介质退化乃至击穿的主要因素,对栅介质中陷阱信息的准确提取和分析将有助于器件性能的优化、器件寿命的预测等。针对几十年来研究人员提出的各种陷阱表征方法,在简单介绍栅介质中陷阱相关知识的基础上,对已有的界面陷阱和氧化层陷阱表征方法进行系统的调查总结和分析,详细阐述了表征技术的新进展。     

带有多层介质衬底FSS的损耗和带宽特性分析

本文简要介绍应用模匹配方法分析带有多层介质衬底的FSS频率响应技术,在此基础上研究带有多层介质衬底的平面Y形缝隙周期阵列对平面波的频率传输特性。重点讨论介质层厚度变化对FSS传输损耗及带宽的影响。     

填充多层介质的共焦椭圆同轴线传播特性

采用在椭圆柱坐标系中分离变量的方法,得到了填充多层介质共焦椭圆同轴线模式特征方程.研究表明:当椭圆退化为圆时,利用角向和径向马修函数的渐进关系,可得到填充多层介质的圆形同轴线的模式特征方程,由此可见,圆形同轴线可看作椭圆形同轴线的特例;当椭圆同轴线内导体半长轴大小为零时,则椭圆同轴线就变成椭圆波导,同样的方法,可得到填充多层介质的椭圆波导模式特征方程.当填充一层介质时,得到了椭圆同轴线和椭圆波导的模式特征方程,结果和相关文献所得结果相同.作为示例,对填充一层介质和两层介质的椭圆同轴线中一些模式色散特性进行了数值计算,分析了椭圆同轴线中介质参数的变化以及椭圆同轴结构的变化等对其传播特性的影响.     

电磁脉冲应力下MOS器件退化失效建模

通过分析电磁脉冲应力下,栅氧化层软击穿(MOS器件主要失效模式)的失效机理,得出结论:它符合基于随机过程的退化失效模型。根据此结论,提出利用该模型来描述电磁脉冲应力下MOS器件的退化失效过程,并给出相应的退化失效模型。同时针对退化失效模型中的失效阈值问题,研究了随机失效阈值问题,分析了周期电磁脉冲应力下MOS器件的失效阈值问题,给出动态应力-强度干涉(SS)I模型。这些为更合理描述和分析MOS器件的退化失效问题提供了新的途径。     

薄栅氧化层相关击穿电荷

栅氧化层厚度的减薄要求深入研究薄栅介质的击穿和退化之间的关系 .利用衬底热空穴注入技术分别控制注入到薄栅氧化层中的热电子和空穴量 ,对相关击穿电荷进行了测试和研究 .结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .提出薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的新观点 .建立了 Si O2 介质击穿的物理模型并给出了理论分析     

薄栅氧化层相关击穿电荷

栅氧化层厚度的减薄要求深入研究薄栅介质的击穿和退化之间的关系.利用衬底热空穴注入技术分别控制注入到薄栅氧化层中的热电子和空穴量,对相关击穿电荷进行了测试和研究.结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡．提出薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的新观点.建立了SiO2介质击穿的物理模型并给出了理论分析.     

Charging damage from plasma enhanced TEOS deposition

Serious n-channel transistor hot-carrier lifetime degradation due to plasma-charging damage during PETEOS deposition is reported for the first time. Contrary to conventional wisdom, a dielectric film thickness dependent damage is observed. A new mechanism for charging-damage during plasma deposition of dielectric is proposed. This new mechanism uses photoconduction to explain why the antennae continue to charge up after a layer of dielectric is deposited on top. Some numerical estimation is provided     

Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences

Experiments were performed to study the effect of line width and length, and the results revealed interesting differences in electromigration behavior of via-fed upper and lower layer dual-damascene test structures. The observed location of electromigration induced void in upper and lower layer test structures cannot be completely explained by the theory of current gradient induced vacancy diffusion. The electromigration median time to failure (MTF) were found to be dependent upon the line width for the lower layer test structures while it remained unaffected in the case of upper layer test structure. Cu/dielectric cap interface acting as the dominant electromigration path and the current crowding location being near the Cu/dielectric cap interface for lower layer structures due to structural differences, explain this behavior. Similarly, short length upper and lower layer test structures exhibited completely different characteristics. The back stress effect on short lines was evident on both upper and lower layer structures, however, only the upper layer showed two distinct via and line failure mechanisms. These observed effects are specific to Cu dual-damascene structures and can have major technological implications for electromigration reliability assessment.     

介质周期结构频率选择特性的多模网络分析

本文采用多模网络与严格模匹配相结合的方法分析了平面波斜入射时介质周期结构的频率选择反射特性。讨论了这种结构全反射的频率、带宽和在确定频带内出现全反射的个数随周期层厚度、附加介质层厚度及介电常数的变化关系,为介质频率选择表面结构的设计提供了依据。最后用平板介质波导理论说明了这种波现象与多层平板介质结构导模色散特性的关系。     

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

Work function tuning of fully silicided NiSi metal gates using a TiN capping layer

This paper investigates a new way of tuning the work function of fully silicided (FUSI) NiSi metal gates for dual-gate CMOS using a TiN capping layer on Ni to control the poly-Si dopant distribution during FUSI formation. In addition, by comparing the work function change of NiSi FUSI with and without TiN capping, we provide clear evidence that dopants at the gate electrode and dielectric interface are responsible for the work function change. The TiN capping layer causes no degradation to the underlying gate dielectric in terms of fixed-oxide charge, gate leakage current, and time-dependent dielectric breakdown characteristics.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Coupling efficiency of front surface and multilayer mirrors as fiber-end reflectors

We examine the efficiency with which light is reflected back into a single-mode fiber by front surface and multilayer dielectric mirrors. Coupling losses are due to the penetration of light into a multi-layer dielectric mirror, fiber-mirror separation, mirror tilt, and polishing-induced curvature of the fiber-end face. We also discuss the degradation of the coupling efficiency due to random errors of the optical layer thickness of dielectric mirrors. The results of this paper are needed for the discussion of the performance of a fiber Fabry-Perot interferometer to he presented in a companion paper.     

Effect of size and plasma treatment and the application of Weibull distribution on the breakdown of PECVD SiNx MIM capacitors

The dielectric breakdown field is one of the important concerns for device reliability. The breakdown of dielectric is originated at a fatal flaw that grows to cause failure and can be explained by the weakest-link theory. In this study, metal-insulator-metal (MIM) capacitors with plasma enhanced chemical vapor deposited (PECVD) SiN_x are prepared. Ammonia (NH₃) plasmas are applied after the deposition of the dielectric SiN_x. The Weibull distribution function, which is based on the weakest-link theory, is employed to analyze the effect of the electrode area as well as the plasma treatment on the breakdown of the MIM capacitors. The time dependent dielectric breakdown testing indicates a decrease in both the leakage current and the lifetime of the MIM capacitors treated with plasma. Possible dielectric degradation mechanisms are explored.     

辐射对准周期多层平板介质栅传输特性的影响

本文多模网络理论与模匹配相结合的方法对准周期多层平板介质栅的传输特性进行了系统的分析，深入讨论了辐射现象对准周期传输特性的影响，为各种介质栅结构的精确设计了依据。     

Improving the dynamic avalanche breakdown of high voltage planar devices using semi-resistive field plates

The problem of breakdown voltage degradation during transient state is well known for SIPOS terminated or passivated devices. The goal of this paper is to physically explain, model and improve the dynamic behaviour of SIPOS terminated diodes. An RC network model for the SIPOS layer will be used. This model is implemented in a circuit simulator and we put in evidence the cause of the problem: the difference in potential repartition between the static and the dynamic mode. In the static mode the potential at the surface of silicon is distributed linearly between the high voltage contact and the anode (grounded), but in dynamic mode, its repartition is almost parabolic. The SIPOS/oxide/silicon structure equivalent circuit is analysed using circuits theory. We prove that the breakdown voltage degradation during transient state is due to the ratio between the SIPOS layer capacitance and the oxide layer one. A solution to improve the dynamic behaviour up to 3000 V/μs is proposed.