半导体和IC

半导体和ＩＣ１４位２ＭＨｚ取样Ａ／Ｄ转换器　　　　　　　查询号２３１Ｄａｔｅｌ公司的ＡＤＳ－９１９是一种高性能１４位２ＭＨｚ取样Ａ／Ｄ转换器，可按照奈奎斯特频率对输入信号进行取样而无遗漏码。ＡＤＳ－９１９具有优异的动态性能，信噪比为７７ｄＢ，总谐波失真为－７４ｄＢ。这种功能完备的ＡＤＳ－９１９采用２４脚ＤＤＩＰ封装，具有快速建立取样保持放大器、Ａ／Ｄ转换器、精密电压基准、定时／控制逻辑和纠锗电路。数字输入和输出电平为ＴＴＬ。ＡＤＳ－９１９采用±１５ｖ（±１２Ｖ）和＋５Ｖ电源，功耗为１．８Ｗ（±１…     

一种含相加器的高速12位D／A转换器

阐述了一种含相加器的高速１２位Ｄ／Ａ转换器的设计和应用，该电路实现Ｉ－Ｖ转换和相加器功能仅用１级视频运效，其内含相加器的小信号带宽为３０～４０ＭＨｚ传输延迟１５ｎｓ该Ｄ／Ａ转换器的稳定时间为２５０ｎｓ，用于压控振荡器时，可获得的高最输出电压仅比＋Ｖｓ低２～３Ｖ，在全温范围内，其线性误差，微分线性误差，相加器线性误差，相加器微分线性误差分别达±１／２ＬＳＢ。     

∑—△A／D转换技术及仿真

∑－△Ａ／Ｄ转换技术近年来颇受重视，因为基于该技术的Ａ／Ｄ转换器能达到很高的分辨率（１６ｂｉｔ以上），并另具一系列优点。本文对∑－△Ａ／Ｄ转换器的基本原理，包括过采样（Ｏｖｅｒｓａｍｐｌｉｎｇ），噪声成形（Ｎｏｉｓｅ Ｓｈａｐｉｎｇ），以及数字抽取滤波（Ｄｉｎｇｉｔａｌ Ｄｅｃｉｍａｔｉｏｎ Ｆｉｌｔｅｒｉｎｇ）等内容，均作了叙述。作者还对一个２０ｂｉｔ∑－△转换器的算法进行了计算机仿真。该转换器     

过采样Σ—Δ A／D转换器

对近采样Σ－ΔＡ／Ｄ转换器作了全面的描述。介绍了Σ－ΔＡ／Ｄ转换器的工作原理，着重推导了转换器中调制器阶数、过采样比和精度的关系，指出了调制器稳定工作的条件。最后，以１８位Σ－ΔＡ／Ｄ转换器稳定工作的条件。最后，以１８位Σ－ΔＡ／Ｄ转换器的调制器设计为例，详细阐述了Σ－ΔＡ／Ｄ转换器的设计过程，并给出了实验结果。     

精密电压基准

查询号：１８７ 数据转换系统的设计之所以是一 个难题，原因之一是系统精度很大程度上依赖于内部或外部ＤＣ电压基准所建立的电压精度。电压基准用来产生一个精确的输出电压，以此为数据转换系统设计满量程输入。在模／数转换器（ＡＤＣ）中，ＤＣ电压基准与模拟输入信号一起用于产生数字化的输出信号。在数／模转换器（ＤＡＣ）中，ＤＡＣ根据呈现在ＤＡＣ输入端上的数字输入信号，从ＤＣ基准电压选择和产生模拟输出。在工作温度范围内基准电压的任何误差将影响ＡＤＣ／ＤＡＣ的线性度和无寄生动态范围（ＳＦＤＲ）。实际上所有电压基准随…     

一种单片12位逐次逼近型A／D转换器研究

本文介绍了一种单片１２位逐次逼近型Ａ／Ｄ转换器。它能在小于６μｓ的转换时间内净０－１０Ｖ或－５－５Ｖ输入的范围的模拟电压转换成相对应的１２位数字输出在码。电路采用ｐ－ｎ结隔离标准３μｍ双极工艺制作，在－４５－＋８５℃温度范围，电路的线性误差和微分线性误差皆小于０．０１２％ＦＳＲ。     

Σ-ΔA/D转换技术及仿真

Σ－ΔＡ／Ｄ转换技术近年来颇受重视，因为基于该技术的Ａ／Ｄ转换器能达到很高的分辨率（１６ｂｉｔ以上），并另具一系列优点。本文对Σ－ΔＡ／Ｄ转换器的基本原理，包括过采样（Ｏｖｅｒｓａｍｐｌｉｎｇ），噪声成形（ＮｏｉｓｅＳｈａｐｉｎｇ），以及数字抽取滤波（ＤｉｇｉｔａｌＤｅｃｉｍａｔｉｏｎＦｉｌｔｅｒｉｎｇ）等内容，均作了叙述。作者还对一个２０ｂｉｔΣ－Δ转换器的算法进行了计算机仿真。该转换器采用了高阶ＭＡＳＨ噪声成形技术，而其数字抽取滤波部分则由梳状滤波器与级联的半带滤波器构成。文章中给出了仿真结果。     

CMOS单片双积分式A／D转换器

ＣＭＯＳ单片双积分式Ａ／Ｄ转换器毕玉国双积分式Ａ／Ｄ转换器转换精度高，抗干扰性好，因此在仪器仪表和测量系统中被大量采用。双积分式Ａ／Ｄ转换器由模拟和数字两大部分电路组成，ＣＭＯＳ单片双积分式Ａ／Ｄ转换器将两部分电路集成在单个芯片内，使用非常方便。本文...     

一种带接口的CMOS10位电流型乘法D／A转换器

介绍了一种带接口的单片ＣＭＯＳ１０位电流型乘法Ｄ／Ａ转换器的设计及工作方式。着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。在不修调电阻网络的情况下，该Ｄ／Ａ转换器在５Ｖ、１５Ｖ下，其线性误差、微分误差、满刻度误差均能达到１０位精度     

一种MCM12位A／D转换器的设计和研制

介绍了一种ＭＣＭ１２位逐次逼近型Ａ／Ｄ转换器ＳＡＤ５０３的特点和工作原理，探讨了它的系统设计、电路设计、工艺技术，阐述了其研制及应用。这种Ａ／Ｄ转换器在３６．５ｍｍ×１０．５ｍｍ的双层薄膜布线陶瓷基板上组装了１８个ＩＣ裸芯片和其他片式器件及电阻网络，并封装于３２引出端双列直插式陶瓷管壳中。线性误差±１／２ＬＳＢ，微分线性误差＜±１ＬＳＢ，转换时间６μｓ，最大功耗８７０ｍＷ     

一种流水线结构A／D转换器的设计

介绍了一种适于数字ＣＭＯＳ工艺实现的优化流水线结构Ａ／Ｄ转换器的设计。并从如何减少误差来源，消除误差影响，减小电路设计难度等方面对该结构进行了详细分析。公式论证和仿真结果表明，采用该方案可实现２０ＭＨｚ工作频率和１０位分辨率的高速高精度、低功耗Ａ／Ｄ转换器。     

一种单片8位高速乘法型D／A转换器

采用硅双极工艺制作了一种单片８位高速乘法型Ｄ／Ａ转换器。该电路具有精度高、速度快、与各种逻辑兼容、使用灵活等特点，在数据采集、数据处理系统、ＣＲＴ、波形产生器、Ａ／Ｄ转换器、伺服马达、ＶＣＤ、可编程电源、音响编码及衰减器、高速调制及解调装置中具有广泛的应用前景。     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/Dconverter

This paper describes a fully monolithic 12-bit, 20 Msample/s, A/D converter. A power dissipation of 250 mW from a single 5 V supply is achieved using a radix=2 pipeline architecture. Linearity and full-scale errors are removed through self-calibration and digital correction with on-chip circuitry. A novel single-ended to differential sample and hold stage is proven to have very good single-ended input performance up to the Nyquist frequency. The total silicon area is 3.2×3.1 mm² in a 0.7 μm CMOS process. Several circuit techniques used in this design together with experimental results are presented     

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-μm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at ±2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of ±0.6 LSB and INL of ±1 LSB at a 12-b resolution have been achieved     

A 12-bit successive-approximation-type ADC with digital error correction

A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 /spl mu/s was obtained with digital error correction.     

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The “split analog-to-digital converter (ADC)” architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of $M$ interleaved ADCs requires $2M + 1$ half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.      

Digital implementation of mismatch shaping in oversampled pipelineA/D converters

Pipeline A/D converters are usually implemented with switched capacitor technology. The effect of gain errors caused by capacitor mismatch may be attenuated using mismatch-shaping techniques. The author introduces an architecture that improves the SFDR of a particular pipeline A/D converter, simply by adding digital hardware to the existing analogue design     

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.