Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Microwave properties and applications of Y–Ba–Cu–O thin films grown on various substrates

Microwave properties of YBa₂Cu₃O_7-δ (YBCO) films grown on (100) LaAlO₃ (LAO), (110) NdGaO₃ (NGO) and (001) SrLaAlO₄ (SLAO) substrates were studied in the form of a microstrip ring resonator at temperatures above 20 K. The YBCO resonator on a SLAO substrate showed microwave properties better than or comparable to other YBCO resonators on LAO substrates. For the YBCO resonators on LAO and SLAO substrates, both Q_U and f₀ appeared to decrease as the temperature was raised. Meanwhile the resonator on a NGO substrate showed different behaviors with Q_U showing a peak at ∼70 K, which are attributed to the unique temperature dependence of the loss tangent of the NGO substrate. An X-band oscillator with a YBCO ring resonator coupled to the circuit was prepared and its properties were investigated at low temperatures. The frequency of the oscillator signal appeared to change from 7.925 GHz at 30 K to 7.878 GHz at 77 K, which was mostly attributed to the change in f₀ of the YBCO ring resonator. The signal power appeared to be more than 4.5 mW at 30 K and 2.1 mW at 77 K, respectively. At 55 K, the frequency of the oscillator signal was 7.917 GHz with the 3 dB-linewidth of 450 Hz.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Distributed NGD active circuit for RF-microwave communication

This paper is aimed to the investigation on innovative distributed negative group delay (DNGD) circuits for RF communication. Thanks to the analogy between the lumped and distributed circuits, NGD circuit topologies were identified. By using the S-parameter theory, analysis and synthesis methods of these topologies are proposed. The DNGD circuits developed are mainly comprised of a transistor combined with a series resistance ended by a stub. Then, synthesis relations enabling to determine the NGD circuit parameters from the desired NGD and gain values are established. As application, an active phase shifter (PS) operating independently with the frequency based on the cascade of PGD and NGD devices was synthesized. First, an NGD PS with transmission phase of (135 ± 5)° around 2.56 GHz over the bandwidth of about 1.02 GHz was obtained. Then, a two-stage DNGD PS exhibiting 90° with ±10° flatness from 4.1 GHz to 6.8 GHz was designed. The DNGD circuit presented can be used in various telecommunication areas notably for correcting RF/numerical signal delays in the RF-microwave analogue-digital devices.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications

A 5 GHz LC VCO (voltage-controlled oscillator) with automatic amplitude control (AAC) and automatic frequency-band selection (AFBS) for 2.4 GHz ZigBee transceivers is presented. Instead of continuous feedback loop, an alternative amplitude calibration scheme is proposed in this paper to alleviate the deficiencies inherent in the conventional approach. It helps to keep the VCO at optimum amplitude to avoid saturation of the cross-coupled transistors and therefore stabilizes the phase noise performance over process, voltage and temperature variations. For the ZigBee application with 16 frequency channels, a coarse tuning loop is added in this work to implement the frequency-band selection using the AFBS mechanism. The VCO core and the digital AAC, AFBS modules have been fully integrated in a 2.4 GHz ZigBee transceiver which was fabricated in a 0.18 μm RF-CMOS technology. The current consumption is 4.7 mA at 4.85 GHz with 1.8 V power supply and a chip area of about 0.285 mm² is occupied. The VCO is capable of operating from 4.67 GHz to 5.18 GHz and the measured phase-noise level is –120 dBc/Hz at 1 MHz offset from a 4.85 GHz carrier. The tuning sensitivity K_VCO of the VCO is about 78 MHz/V with 0.9 V control voltage.     

A new ultra low-power,universal OTA-C filter in subthreshold region using bulk-drive technique

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans-resistance and trans-conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I_a = 50 nA, I_b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans-conductance (g_m) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter.     

Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

Microwave dielectric properties of (1 − x)(Mg0.95Co0.05)TiO3– xCa0.6La0.8/3TiO3 ceramics with V2O5 addition

The microstructures and the microwave dielectric properties of the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system were investigated. In order to achieve a temperature-stable material, we studied a method of combining a positive temperature coefficient material with a negative one. Ca_0.6La_0.8/3TiO₃ has dielectric properties of dielectric constant ε_r ∼ 109, Q × f value ∼ 17,600 GHz and a large positive τ_f value ∼ 213 ppm/°C. (Mg_0.95Co_0.05)TiO₃ ceramics possesses high dielectric constant (ε_r ∼ 16.8), high quality factor (Q × f value ∼ 230,000 GHz), and negative τ_f value (−54 ppm/°C). As the x value varies from 0.1 to 0.8, (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system has the dielectric properties as follows: 21.55 < ε_r < 75.44, 21,000 < Q × f < 90,000 and −10 < τ_f < 140. By appropriately adjusting the x value in the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system, zero τ_f value can be achieved. With x = 0.15, a dielectric constant ε_r ∼ 25.78, a Q × f value ∼ 84,000 GHz (at 9 GHz), and a τ_f value ∼ 2 ppm/°C were obtained for 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics sintered at 1400 °C for 4 h. For practical application in communication systems, it is desirable to be able to sinter at lower temperatures. Therefore, V₂O₅ was as a sintering aid for lowering the sintering temperature of0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics. At the same time, the 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramic system with 0.5 wt% V₂O₅ can be obtained good properties at the microwave frequencies for 1200 °C.     

High-resolution wide-band LC-VCO for reliable operation in phase-locked loops

This paper presents a novel sizing scheme to implement the array of switches in the capacitor bank of LC-VCOs for oscillation frequency coarse control. The proposed scheme allows increasing the number of elements in the capacitor bank beyond the values typically achieved by binary scaling, endowing the resulting LC-VCO with a wider tuning range and high frequency resolution, which is beneficial for the implementation of reliable phase-locked loops. Two different gigahertz LC-VCOs have been designed to validate the proposed scheme. The prototypes, fabricated in a cost-effective 0.18 μm CMOS process, cover a 700 MHz frequency range from 1.35 GHz to 2.05 GHz and from 2.05 GHz to 2.75 GHz, respectively, with a phase noise figure of − 122 dBc/Hz and − 119.5 dBc/Hz at 1 MHz from the mid-range carriers, and a power consumption of 18 mW. These figures result in a respective FOM_T of − 186.4 dBc/Hz and − 183.8 dBc/Hz. The performance of the fabricated LC-VCOs is achieved in each case with a dense coarse tuning range of 128 levels, which allows, respectively, a fine tuning gain smaller than 40 MHz V^− 1.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

Improved performance step impedance lowpass filter

Performances of the conventional Butterworth step impedance lowpass filters (LPF) are significantly improved by placing transmission zero either closer to the cut-off frequency (f_c) or away from it. It is achieved by using transverse resonance width of the capacitive line sections. We report method of designing transverse resonance type LPF (TR-LPF) for 5 to 11-pole filters. At f_c = 2.5 GHz, we obtained selectivity in the range 113.3–56.66 dB/GHz and 20–60 dB rejection BW in the range 9.61–7.29 GHz. The TR-LPF can suppress the stopband signal by 60 dB up to 5f_c. Insertion loss in passband is within 0.72 dB. Improved performance of TR-LPF can be designed for f_c up to 7.5 GHz.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.