A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications

A 5 GHz LC VCO (voltage-controlled oscillator) with automatic amplitude control (AAC) and automatic frequency-band selection (AFBS) for 2.4 GHz ZigBee transceivers is presented. Instead of continuous feedback loop, an alternative amplitude calibration scheme is proposed in this paper to alleviate the deficiencies inherent in the conventional approach. It helps to keep the VCO at optimum amplitude to avoid saturation of the cross-coupled transistors and therefore stabilizes the phase noise performance over process, voltage and temperature variations. For the ZigBee application with 16 frequency channels, a coarse tuning loop is added in this work to implement the frequency-band selection using the AFBS mechanism. The VCO core and the digital AAC, AFBS modules have been fully integrated in a 2.4 GHz ZigBee transceiver which was fabricated in a 0.18 μm RF-CMOS technology. The current consumption is 4.7 mA at 4.85 GHz with 1.8 V power supply and a chip area of about 0.285 mm² is occupied. The VCO is capable of operating from 4.67 GHz to 5.18 GHz and the measured phase-noise level is –120 dBc/Hz at 1 MHz offset from a 4.85 GHz carrier. The tuning sensitivity K_VCO of the VCO is about 78 MHz/V with 0.9 V control voltage.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.     

A quadrature RC-oscillator with capacitive coupling

In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the power dissipation. The results show that a phase error below 1° and an amplitude mismatch lower than 1% are obtained with a coupling capacitance about 20% of the oscillator׳s capacitance value. Due to this kind of coupling, the phase-noise improves by 3 dB (to −115.1 dBc/Hz @ 10 MHz) and the increase of power requirement is only marginal leading to a figure-of-merit of −154.8 dBc/Hz. This is comparable to the best state-of-the-art RC-oscillators, yet the dissipated power is about four times less. We present calculations of frequency, phase error and amplitude mismatch that are validated by simulations. The theory shows that phase error is proportional to the amplitude mismatch, indicating that an automatic phase error minimization based on the amplitude mismatches is possible. The measurements on a 2.4 GHz voltage-controlled quadrature RC-oscillator with capacitive coupling fabricated in 130 nm CMOS circuit prototypes validate the theory.     

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCO's output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35 µm process show a linear tuning range improvement of 75% of the control voltage in the (1.43–1.55) GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from −94 dBc/Hz to −124 dBc/Hz @600 kHz offset from the carrier with an overall reduced amplitude noise for the VCO.     

Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

The voltage-controlled oscillator (VCO) in frequency-based $\Updelta\Upsigma$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving ?125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670???W at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $\Updelta\Upsigma$ modulator.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960 MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21 dBm output power and 35% power-added efficiency (PAE) with 3 V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.     

Low-harmonic distortion in single-ended and push-pull class E power amplifier by using slotted microstrip lines

In this work, a very low-harmonic distortion with high power-added efficiency (PAE) power amplifier (PA) with slotted microstrip lines is reported. The circuit is a push-pull class E amplifier, terminated with defected structures to improve the spectrum purity and efficiency. The relationship of the second and third harmonic to the fundamental is 70 and 54 dBc, respectively. The amplifier is developed with HBT medium power transistors. The circuit works at 1.8 GHz obtaining a PAE close to 60%, delivering an output power of 24 dBm with a power gain of 13.3 dB.     

A compact and low-phase-noise Ka-band pHEMT-based VCO

A low phase-noise Ka-band monolithic voltage-controlled oscillator (VCO) designed using the negative resistance concept is reported. A circuit fabricated using the three-dimensional monolithic microwave integrated circuit technology exhibits a high integration level; its size is a record at just 0.5 mm/sup 2/. On-wafer measurements demonstrate a low phase noise of -102 dBc/Hz at a 1-MHz offset. The VCO delivers an output power of 11.8 dBm at the center frequency of 28.3 GHz. The frequency tuning range is more than 3.8 GHz. Dependence of the circuit performance on the bias conditions is also reported and suggests that an optimum phase-noise characteristic can be achieved when biasing the transistor to optimize its transconductance and noise figure.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A novel wide band super transistor based voltage feedback current amplifier

This paper is assigned to the design of voltage feedback current amplifiers (VFCAs). Their operation and interesting characteristics are covered and a novel CMOS VFCA is presented. New ideas based on super transistors (STs) are devised and used to design a high performance VFCA. Benefiting from the interesting properties of STs, the proposed VFCA exhibits high linearity, high output impedance, very low input impedance and wide bandwidth. The proposed circuit is designed using TSMC 0.18 μm CMOS technology parameters and supply voltage of ±0.75 V. Simulation results with HSPICE show low THD of ?60 dB at the output signal, very low impedance of 0.6 Ω and 0.2 Ω at the input and feedback ports respectively and high output impedance of 10 MΩ. Moreover it can provide wide ?3 dB bandwidth of 15.5 MHz. The results prove the high capability of the VFCA in current mode signal processing and encourage strong motivation to develop commercially available VFCAs.     

Phase-Noise Improvement of GaAs pHEMT K-Band Voltage-Controlled Oscillator Using Tunable Field-Plate Voltage Technology

This letter presents a voltage-controlled oscillator (VCO) with low phase-noise performance by applying tunable field-plate (FP) voltage on 0.15-mum-gate-length GaAs pseudomorphic high-electron-mobility transistors (pHEMTs). In this letter, the FP metal between gate and drain terminals was connected to a single pad and was controlled by an extra voltage supplier (V_FP). Owing to the depth modulation of FP-induced depletion region at various FP voltages, the device flicker noise was also improved by applying negative V_FP. This technique is convenient to be applied in standard pHEMT fabrication and particularly attractive for reducing the phase noise of VCO design without extra power consumption. A tunable phase-noise inductor-capacitor feedback 21-GHz VCO was demonstrated. The measured phase noise of this novel design is -95 dBc/Hz at an offset frequency of 1 MHz, and this value can be improved to -99.6 dBc/Hz at V_FP of -5.5 V. The core dc-power consumption of this circuit is 30.8 mW.     

Dual-resonance concurrent oscillator

This paper studies a new dual-band CMOS class-C voltage-controlled oscillator (VCO). The oscillator consists of a dual-resonance LC resonator in shunt with two pairs of capacitive cross-coupled nMOSFETs. The proposed oscillator has been implemented with the TSMC 0.18 μm CMOS technology, and it shows a frequency tuning range with two frequency bands and a small tuning hysteresis is measured. The oscillator can generate differential signals at 2.4 GHz and 6.9 GHz and it also can generate concurrent frequency oscillation while the circuit is biased around the bias with frequency tuning hysteresis. With the supply voltage of V_DD = 1.1 V, the VCO-core current and power consumption of the oscillator are 2.90 mA and 3.19 mW, respectively. The die area of the class-C oscillator is 0.9 × 0.97 mm². Overvoltage stress is applied to the oscillator, measurement indicates the concurrent oscillation is sensitive to overvoltage stress.