A versatile 16-channel front-end integrated circuit for semiconductor radiation detectors

A CMOS front-end integrated circuit consisting of 16 identical analog channels is proposed for semiconductor radiation detectors. Each of the 16 channels has a low noise charge sensitive amplifier, a pulse shaper, a peak detect and hold circuit and a discriminator, while analog voltage and channel address are routed off the chip. It can accommodate both electron and hole collection with selectable gain and peaking time. Sequential and sparse readout, combining with self-trigger and external trigger, makes four readout modes. The circuit is implemented in a 0.35 μm DP4M (double-poly-quad-metal) CMOS technology with an area of 2.5×1.54 mm2 and power dissipation of 60 mW. A single channel chip is tested with Verigy 93000. The gain is adjustable from 13 to 130 mV·fC–1 while the peaking time varies between 0.7 and 1.6 μs. The linearity is more than 99% and the equivalent noise charge is about 600e.     

基于3D Si PIN阵列热中子探测器的变增益宽动态前端读出电子学设计

基于Si CMOS技术的前端读出ASIC主要是根据3D Si PIN阵列热中子探测器的输出信号特性设计的。所设计的读出ASIC的主要电路模块包括电荷灵敏放大器（CSA）、模拟开关设计、具有三级电荷灵敏自动转换的自动增益控制模块（AGC）、相关双采样（CDS）和基准电流源电路。仿真结果表明,前端电路的输入动态范围为10 fC~80 pC。根据热中子探测器输出信号特性设计的ASIC的3个增益系数分别为19 V/pC、039 V/pC和94 mV/pC。所设计的ASIC的积分非线性小于 1%。单通道静态功耗约为 536 mW。零输入探测器电容时的等效噪声电荷为2416e-。计数率可达1 MHz 。     

Design and performance of a low-noise, low-power consumption CMOS charge amplifier for capacitive detectors

In this paper, a new design of low noise, low-power consumption charge amplifier is described. Theoretical results show that a total output noise voltage reduction of 0.261 mV has been obtained. This value corresponds to a 46% reduction compared to the noise performance of a conventional charge amplifier. A complete readout system including the proposed charge amplifier has been realized in a 0.8-/spl mu/m semiconductor on insulator (SOI) bipolar complementary metal-oxide-semiconductor (BiCMOS) process. A measured noise performance of 450 electrons at 0 pF with a slope of 44 electrons/pF for a shaping time of 45 ns, a conversion gain of 20 mV/fC and 1-mW power consumption have been obtained.     

CsI(Tl)闪烁探测器读出电路设计

介绍了配置于新型γ能谱仪的CsI(Tl)闪烁探测器的读出电路设计。输入缓冲级采用折叠嵌位电路,改善了系统频率特性并提高了输入阻抗;放大级采用自举电路,改善了系统动态性能并提高了开环增益;输出级采用电流源负载电路,改善了输出信号的线性度并增强了系统的稳定性。实验表明:读出电路噪声为51.08 f C+1.97 f C/p F,时间漂移为0.112%,探头对137Cs源γ射线的输出信号信噪比可达23:1,能量分辨率可达4.98%。     

带增益的气体探测器读出ASIC的研制

设计了用于带增益的气体探测器比如GEM、RPC等读出的ASIC,实现对探测器信号的放大、成形和对后续实时采样ADC的驱动电路.电荷增益和成形时间可调,有利于探测器不同增益下性能的研究,也扩展了芯片的应用范围.由于成形电路引入的噪声变得显著,在低电荷增益下,ENC会随增益下降而增加.芯片采用Chartered 0.35μm2P4M CMOS工艺,论文介绍了芯片的详细设计和仿真结果.     

半导体阵列微剂量探测器前端读出电路设计

根据三维Si SOI PIN像素微剂量探测器特性参数,设计了一种基于GF chrt018IC CMOS工艺的前端读出电路。该读出电路主要包括PMOS输入的电荷灵敏前前置放大器,有源整形滤波电路,电压比较器及基准电流源等,可实现对微剂量信号的放大、滤波降噪、甄别输出等功能。仿真测试表明:能量探测范围为5~500 fC,单通道功耗约为2 mW,总噪声性能为0.05 f C+1.6×10~(-3)fC/pF。     

RG64—High Count Rate Low Noise Multichannel ASIC With Energy Window Selection and Continuous Readout Mode

We report on the performance of a low noise and high count rate readout ASIC with binary architecture and energy window selection for X-ray imaging applications using semiconductor detectors. The ASIC called RG64 is designed in 0.35 mum CMOS process and its total area is 3900times5000 mum². The core of RG64 consists of 64 readout channels. Each channel is built of a charge sensitive amplifier with a second order shaper of peaking time 75 ns, two independent discriminators with an 8-bit offset correction circuit and two independent 20-bit counters with RAM memory buffers. The ENC of the circuit reaches the value of about 126 el. rms with 1 pF input load and 5 mW power consumption per single channel. The mean gain in the multichannel ASIC is about 50 muV/el., with the dispersion from channel to channel of 0.9% (on one sigma level). The deviation of the effective threshold voltage spread for given energy can be reduced to less than 7 el. rms (calculated to the charge sensitive amplifier input). High count rate measurements have been performed up to 2 Mcps of average rate of input pulses, both for AC and DC coupled silicon strip detectors with X-ray photons of energy 8.04 keV. The RG64 can operate both in the continuous readout mode and in the readout mode separate from exposure.     

RX64DTH -a fully integrated 64-channel ASIC for a digital X-ray imaging system with energy window selection

We report on the multichannel IC (RX64DTH) designed for position sensitive X-ray measurements with silicon strip detectors and dedicated to medical imaging applications. This integrated circuit has a binary readout architecture with a double threshold allowing on selection energy window for measured signals. The design was realized in a 0.8 /spl mu/m CMOS process. The core of the RX64DTH IC consists of 64 readout channels. The single channel is built with four basic blocks: charge sensitive preamplifier, shaper, two independent discriminators, and two independent 20-bit counters. Each readout channel counts pulses which are above the low discriminator threshold and counts pulses independently above the high discriminator threshold. The energy resolution in such architecture is limited by the noise of a single channel and by channel to channel threshold spread. We present the noise and matching performance of a 384-channel module built with a silicon strip detector and six RX64DTH ICs. In the 384-channel module an equivalent noise charge of about 200 el. rms is achieved for the shaper peaking time of 0.8 /spl mu/s and strip capacitance of 3 pF. The deviation of discriminator thresholds for the whole system is only 87 el. rms. The obtained results show that the energy resolution and uniformity of analog parameters (noise, gain, offset) are sufficient for medical diagnostic applications such as dual energy mammography and angiography.     

共面栅碲锌镉探测器读出电路设计及性能研究

为有效读出共面栅碲锌镉(CPG-CZT)探测器的核脉冲信号，本文结合CPG-CZT探测器工作原理及国内外研究，设计了可用于CPG-CZT探测器的读出电路，主要包括高压偏置电路、前置放大电路、增益调节及减法电路。为研究读出电路性能，本文测试了各单元电路的性能及探测系统能量分辨率随偏置电压、增益调节电路中两路信号的相对增益G的变化规律。结果表明：高压偏置电路两路输出偏压与输入偏置电压的相关系数R²均为0.998；前置放大电路输出噪声为5 mV；增益调节及减法电路输出信号噪声为10 mV；输入偏置电压、相对增益G的变化均会影响探测系统能量分辨率，当偏置电压为-1650 V、相对增益G为0.7时对¹³⁷Cs源产生的γ射线能量分辨率最佳，可达3.65%，且无明显拖尾现象。     

ICON, a current mode preamplifier in CMOS technology for use withhigh rate particle detectors

The ICON current mode preamplifier intended for use in experiments at high-rate hadron colliders is described. The transient response and noise performance are analyzed. One chip has been made using an ICON circuit with resistive feedback to produce a preamplifier with a peaking time of below 10 ns. This fast preamplifier has a gain of 870 mV/pC and a power dissipation of around 1 mW. Another chip was made using the ICON circuit as the front-end to a dual-port analog memory. The noise measured is between 2400 e^- and 3000 e^-. An important characteristic of ICON is that it can tolerate a detector leakage current of 10 μA at the DC-coupled input. Therefore, it is very suitable for silicon detector systems under severe radiation conditions     

Characteristics of 16-Channel ASIC Preamplifier Board for Microstrip Gas Chamber and Animal PET

A 16-channel ASIC preamplifier board has been designed for microstrip gas chamber (MSGC) and animal position emission tomography (PET) detectors. The highly integrated ASIC chips can be used for individual readouts from a large number of channels to improve the spatial resolution and counting rate. The preamplifier board was tested to have a low optimum equivalent noise charge (ENC) of ~ 1400 e^? FWHM at a shaping time of 0.1 μs. The output voltage to input charge gain is 0.96 V/pC, and the nonlinearity is ~ 2:0% over a range of ?500 fC to 1000 fC in input charge. The rise time (10%–90%) with no input capacitor is about 54 ns. The power consumption of this preamplifier board is ~ 100 mW. The preamplifier board has been used to read out a 3 × 3 cm MSGC plate and an optimum FWHM energy resolution of 19.1% (5.9 keV peak of Fe-55) was obtained.     

微结构气体探测器多通道高速读出系统研制

本文设计并实测了用于多通道微结构气体探测器信号读出的512通道电子学系统。该系统以Spartan-6 FPGA作为控制和数据处理核心，使用4通道ADC芯片对4片APV25芯片的输出信号进行同步模数转换，经千兆以太网发送命令和传输数据，计算机端则以双线程分别接收和发送数据。实测输入电容低于200 pF时，系统噪声低于2000e，有效电荷输入范围为±20 fC，12 fC以下时线性良好。经长时间测试，系统稳定可靠，千兆网数据传输速率可达940 Mb/s。单片APV25工作时，连续触发率可达APV25上限285 kHz，4片时则为134 kHz。在实际应用于GEM探测器α射线成像实验中取得了较好的成像结果。     

Performance of an ASD-8 based wire chamber readout system

For the medium-energy proton polarimeter mounted at the focal-plane of the Big-Bite Spectrometer at Kernfysisch Versneller Instituut Groningen, a new wire-chamber readout has been developed. The charge-sensitive preamplifier is based on the ASD-8 B chip which has an input impedance of 115 Ω. This low impedance and the short integration time of 6 ns at a usable sensitivity of 5 fC allow high readout rates and low gas amplifications. This front-end circuit is mounted on all four multi-wire proportional chambers and on two vertical-drift chambers with 3872 wires in total. Measurements have been made using sources and intermediate energy protons. Special attention was given to determine the time-over-threshold properties of the circuit. The time-over-threshold capabilities of the readout system extend future applications to particle discrimination, or, in connection with other detector types, to energy-resolving readout. The operational performance of the readout system is presented     

DAMPE-PSD读出电子学研制

暗物质粒子探测卫星(dark matter particle explorer, DAMPE)是我国空间科学卫星系列的首发星，用于找出可能的暗物质粒子信号。塑料闪烁体阵列探测器(plastic scintillator detector, PSD)分系统作为卫星有效载荷的主体部件之一，参与承担高能粒子电荷测量和电子/γ射线鉴别任务。PSD由82根塑料闪烁体条和164个光电倍增管（photomultiplier tube, PMT)组成，有328个输出通道，每根塑料闪烁体条的动态范围为2×103，需配备1套完备的读出电子学系统。该电子学系统由4块前端电子学（front-end electronics, FEE）板构成，共具有360个信号处理通道，总功耗6 W。电路主要包括电荷测量电路、模拟调理电路、模数变换电路、刻度电路、环境监测电路、FPGA电路、电源管理电路以及接口电路等，其主要功能是基于32路模拟信号将PMT的电荷信号输入VA160 ASIC芯片，考虑了抗辐照加固、温度设计等一系列关键问题，以确保在严酷的太空中具有长期的可靠性。测试结果表明，该FEE系统工作稳定、性能良好，具有较好的技术指标，每个电子学通道实现了0～12.5 pC的动态范围，通道的随机噪声水平好于2 fC，积分非线性好于0.6%。FEE能适应恶劣的空间环境，具有很高的可靠性。FEE配合PSD样机还分别于2014年和2015年在欧洲核子中心（CERN）的PS和SPS终端成功完成了2次束流试验，验证了PSD的探测能力完全满足任务书中提出的功能和指标要求，能很好实现实际科学任务需求。     

Design and Characterization of a Low Power Consumption, HPGe Spectrometer

A low power consumption, high resolution germanium spectrometer is described. The spectrometer consists of an HPGe detector (either conventional or reverse electrode), a charge loop amplifier, a high count rate indicator, detector bias shutdown electronics, and a portable cryostat. A brief analysis of the charge loop amplifier is presented. Data for FET noise at reduced drain currents is also presented. The effects of various circuit components on temperature coefficient of gain are described along with measured temperature coefficient. Finally, the resolution and peak shift versus count rate are presented along with the spectrometer configuration.     

高计数率气体探测器读出电子学原型机研制

研制一套可用于高计数率气体探测器的读出电子学原型机系统,包括前端板、数据采集板和上位机。前端板采用一款先进的前端读出专用集成电路(ASIC)芯片实现对探测器信号的测量和模数转换;数据采集板利用现场可编程门阵列（FPGA）实现对数据的分析、处理和传输;上位机实现控制指令发送、PC端数据接收及存储等。在22~99 fC的输入范围内,原型机各通道积分非线性均好于024%;联合探测器使用55Fe放射源测试,结果好于相同条件下的商用电子学。可满足20 kHz计数率下GEM TPC探测器的读出需求。     

新型电荷灵敏前置放大器研制

基于Multisim软件仿真,研制了一种新型电荷灵敏前置放大器,其输入缓冲器采用JFET构成的共源共栅电路,放大级电路采用集成运算放大器。经测试,信号上升时间为85ns;当RC成形时间为10μs时,零电容噪声为970e,噪声斜率为7.40 e/p F,对~(137)Cs源γ射线测量信噪比为32:1。     

大动态范围多通道电荷测量系统的研制

基于新型探测系统的特点,利用挪威IDEAS公司的电荷测量芯片Viking Chip构建一个大动态范围(0-13pC)、多通道(每个模块32通道以上)、高精度(所有通道的噪声均方差在1.2-1.4fC)的电荷测量系统,最大可测信号和噪声的比值达104。     

基于APV25多通道读出电子学系统设计

介绍了基于APV25芯片的多通道读出电子学系统的设计方法,利用ASIC芯片与可扩展读出系统相结合,实现多通道信号的处理。在该系统中,基于PXI机箱的单个读出板可实现2 048路信号的读出及处理,并具有集成度高、低功耗、可扩展等优点。电子学测试结果表明,本系统电荷输入线性动态范围为0~12 fC,APV25等效输入噪声408 e,可适应大型物理实验微结构气体探测器、硅像素探测器等探测器的读出需求。     

硅像素探测器读出芯片的设计

针对应用在高能物理实验的硅像素探测器,设计了一种基于时间过阈技术的像素阵列读出芯片。芯片采用商用的130 nm CMOS工艺进行流片,共有30×10个像素单元,像素单元的面积为50 μm×250 μm。测试结果表明,像素单元电路的等效噪声电荷低于100e^-,积分非线性优于4.2%,基本实现了设计的功能。