Failure study of Sn37Pb PBGA solder joints using temperature cycling,random vibration and combined temperature cycling and random vibration tests

In this paper, the tin-lead (Sn-37wt%Pb) eutectic solder joints of plastic ball grid array (PBGA) assemblies are tested using temperature cycling, random vibrations, and combined temperature cycling and vibration loading conditions. The fatigue lives, failure modes for the solder joints and the typical locations of the failed solder joints for single-variable loading and combined loading conditions are compared and analyzed. The results show much earlier solder joint failure for combined loading than that for either temperature cycling or pure vibration loading at room temperature. The primary failure mode is cracking within the bulk solder under temperature cycling, whereas the crack propagation path is along the intermetallic compound (IMC) layer for vibration loading. The solder joints subjected to combined loading exhibit both types of failure modes observed for temperature cycling and vibration loading; in addition, cracking through the IMC and the bulk solder is observed in the combined test. For temperature cycling and vibration loading, the components in the central region of the printed circuit board (PCB) have more failed solder joints than other components, whereas for combined loading, the number of failed solder joints in the components in different locations of the PCB is approximately the same.     

Novel failure mode of chip corrosion at automotive HALL sensor devices under multiple stress conditions

Semiconductor devices used in automotive applications undergo numerous stress situations depending on their particular application. Corrosion, as one main crucial failure mechanisms, can affect the lifetime of electronic components on system, device or even die level. In this paper, a novel corrosion mechanism on HALL sensor devices is investigated and clarified. This corrosion is only occurring under complex conditions like layout aspects, ionic impurities combined with humidity penetration and thermo-mechanical strain due to packaging and additional mechanical load from further over moulding. It is shown how advanced physical and chemical analysis can be combined with finite element simulation to ascertain a chemical degradation running on silicon, silicon dioxide and metallisation level to derive the complete chemical reaction mechanism for the observed corrosion defects. To verify the new failure mode, experiments to recreate this type of corrosion were carried out. Finally, conclusions are drawn on how failure modes can be prevented and how the robustness of the HALL devices under harsh environments can be increased.     

Modeling of Combined Temperature Cycling and Vibration Loading on PBGA Solder Joints Using an Incremental Damage Superposition Approach

Concurrent vibration and temperature cycle environments are commonly encountered in the service life of many electronic products, particularly those used in automotive, avionic, and military applications. However, the ability to predict life expectancy under these types of environments remains a technical challenge. In this paper, a traditional linear damage superposition modeling approach and a damage superposition approach that considers the temperature imposed load state on vibration damage are compared with experimental test results for plastic ball grid array (PBGA) assemblies subjected to temperature cycling, vibration loading, and combined temperature cycling and vibration loading conditions. The results showed much earlier PBGA solder-joint failure under combined loading than with either separate temperature cycling or room temperature vibration loading. Traditional linear superposition was found to over-predict the solder-joint fatigue life, since it neglects the interaction effects of two different loadings. The damage superposition approach that considers the temperature imposed load state on vibration damage is found to be more representative of test data.      

A Rapid Life-Prediction Approach for PBGA Solder Joints Under Combined Thermal Cycling and Vibration Loading Conditions

While some electronic products are routinely subjected to concurrent vibration and temperature cycle loading, the ability to accurately model and estimate life expectancy of hardware under such conditions still presents a unique challenge. For combined vibration and temperature cycling, one of the most likely causes of failure is the fatigue of solder interconnects. This paper presents an approach to predict solder joint life under combined thermal cycling and vibration loading conditions, by taking into account temperature effects and loading interactions. Combined loading experiment on a test vehicle populated with PBGA packages was used to demonstrate this approach.      

Power cycling on press-pack IGBTs: measurements and thermomechanical simulation

Press-pack IGBTs are increasing their market-share, especially for traction applications. As packaging performance is a key factor for a successful product, there is a great interest in defining optimal solutions in terms of geometry, materials and mechanical loading. To support IGBT reliability assessment we developed a testing rig for accelerated testing of a single chip under controlled pressure conditions. In parallel, we created a thermomechanical simulation of the chip/testing rig assembly for the determination of internal stresses and strains due to actual operation. Test results and preliminary failure analysis following power cycling show the possibility of predicting the degradation according to different mechanisms induced by the combined effect of pressure and temperature fluctuation.     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

Reliability of CSP Interconnections Under Mechanical Shock Loading Conditions

Failure modes and mechanisms under mechanical shock loading were studied by employing the statistical and fractographic research methods, and the finite element (FE) analysis. The SnAgCu-bumped components were reflow-soldered with the SnAgCu solder paste on Ni(P)|Au-coated and organic solderability preservative-coated multilayer printed wiring boards with and without micro-via structure in the soldering pads. The component boards were designed, fabricated, assembled, and drop tested according to the JESD22-B111 standard for portable electronic products. The test data were analyzed by utilizing the Weibull statistics, and the characteristic lifetimes (eta) and shape parameters (beta) were calculated. Statistically significant differences in the reliability were found between the different coating materials and pad structures. The results on the failed assemblies showed good correlation between the failure modes and the FE calculations. Under high deformation rates the solder material undergoes strong strain-rate hardening, which increases the stresses in the interconnections as compared to those in the thermal cycling tests. Therefore, the failure mechanisms under high deformation rates differed essentially from those observed in thermal cycling tests     

电子产品可靠性评价与物理模型应用探讨

该文以电子产品的故障为出发点,从集成电路-封装、集成电路-芯片、电路板(或线路板)、电子元件、系统和多系统的角度论述了不同任务环境下电子器件的故障机理特点。系统论述了故障模式、影响及危害性分析(FMECA)和故障模式、机理与影响分析(FMMEA)两种故障机理分析方法,同时结合低周疲劳、高周疲劳、裂纹萌生、反应论模型、芯片失效等失效机理对故障物理元模型进行分类讨论,对电子产品可靠性评价与物理模型应用进行了系统的探讨,为电子产品可靠性评价及失效物理评估模型的选取提供了依据。     

真空电子器件的失效模式及原因分析

通过研究真空电子器件可靠性的国内外动态,发现国产真空电子器件的可靠性与国际先进水平相比还存在较大的差距.为了寻找改进的切入点,从器件结构和使用环境两方面讨论了国产真空电子器件的常见失效模式及其失效原因,为进一步地开展国产真空电子器件的可靠性研究进行有益的探索.     

A novel accelerated test technique for assessment of mechanical reliability of solder interconnects

New generations of lead-free solder interconnects are widely used in consumer electronics. Reliability of the devices which are subjected to rough handling, depends on the fracture resistance of the solder interconnects to shock and mechanical loading. The conventional reliability testing procedures are reported to be expensive and time consuming. Thus alternative tests and evaluation methods for reliability assessment of solder joints are required. In this study a new method for quality assessment of solder interconnects under high strain vibrational shear loading is presented using an ultrasonic fatigue testing system in combination with a special experimental set-up. Using this technique lifetime curves for solder ball bonds of two different Sn–Ag–Cu lead-free alloys were obtained. Failure mechanisms of the solder ball bonds were studied using SEM methods and the reliability curves were discussed with regard to the failure modes and the composition of the lead-free alloys. The applicability of the proposed method is discussed with regard to the literature data.     

Operating limits for RF power amplifiers at high junction temperatures

LDMOS RF––power amplifier components usually operate under severe conditions challenging long-term reliability. These components are subjected to high power dissipation and consequently high junction temperatures. Failure mechanisms are highly temperature dependent and driven by coupled electro-thermo-mechanical fields as a function of stress time. In this work we have investigated the reliability of such a component. Power cycling was used to assess its reliability by introduction of temperature gradients and transient at elevated junction temperatures. The experimental lifetime acceleration conditions provided transient thermal constraints to the thermo-mechanical strength of the silicon die. Power dissipation has been adjusted to cover a broad temperature range (T_{j max}: 200–300 °C) in the peak of a single power cycle. Different failure modes have been observed and related to the different temperature ranges. The experimental results have been combined with thermo-mechanical FE-simulations in ANSYS, leading to the validation of simulation models and implementation in a larger simulation network. The power cycling approach as applied in this paper provided a useful addition to the steady state reliability information. In this way, clear information about margins for safe operation under dynamical conditions has been obtained. This information is needed to fully exploit the functional capability of the component and avoid over-specification in the final application. Overall, the LDMOS RF–PA component showed excellent reliability which makes it suitable for application in telecom devices.     

Thermomechanical reliability characterization of a handheld product in accelerated tests and use environment

Thermomechanical reliability of electronics has commonly been studied by employing accelerated temperature cycling (ATC) tests. However, due to the localized heat dissipation in modern electronic devices, operational power cycling (OPC) is considered a more realistic testing alternative. In order to characterize the thermomechanical reliability of modern high-density electronics, the failure modes, mechanisms and lifetimes of a contemporary commercial handheld device were studied under the ATC and OPC conditions.The experimental measurements and finite element analysis (FEA) showed distinct differences in the thermomechanical response of the device component boards under the OPC and ATC conditions. The results from FEA showed that the interconnection deformations during the OPC test were mostly in the elastic region of the solder, whereas those during the ATC tests reached well into the plastic region. The inclusion of the product enclosure further emphasized this difference, as the enclosure restricted the thermal expansion of the component board during OPC testing. The experimental test results were consistent with the FEA results, as the device failed due to solder interconnection cracking under the ATC conditions within 18 days of testing, but those under the OPC conditions remained operational even after 460 days.Finally, FEA estimations suggest that even three times higher power dissipation levels compared to those found in contemporary handheld devices would result in many years of lifetime in OPC testing.     

A fast mechanical test technique for life time estimation of micro-joints

A novel accelerated mechanical testing method for reliability assessment of micro-joints in the electronic devices is presented as an alternative to time consuming thermal and power cycling test procedures. A special experimental set-up in combination with an ultrasonic resonance fatigue testing system and a laser Doppler vibrometer is used to obtain fatigue life curves of micro-joints under shear loading. Using this method fatigue life curves of Al wire bonded micro-joints were obtained up to 10⁹ number of loading cycles and discussed with regard to micro-mechanisms of the bond failure. Failure analysis of the fatigued micro-joints showed that the predominant failure mechanism of power cycling tests, bond wire lift-off, was reproduced by the mechanical testing procedure. Life time of the micro-joints was modelled using a Coffin–Manson type relationship and showed a good correlation to life time curves obtained by power cycling tests. The major advantage of the proposed fast mechanical testing method is the significant reduction of the testing time in comparison with conventional thermal and power cycling tests. Furthermore subsequent examination of the failure surface provides a reliable tool for improvement of the bonding process. The proposed high frequency fatigue testing system can be applied as a rapid qualification and screening tool for various kinds of interconnects in electronic packaging.     

Historical overview and future of optoelectronics reliability for optical fiber communication systems

The failure modes and failure mechanisms in optoelectronic devices, such as laser diodes, Light-emitting diodes, and photodiodes, are reviewed through a historical overview of device reliability and their future reliability is briefly discussed.     

Requirements in power cycling for precise lifetime estimation

This paper discusses power cycling as a method to evaluate the reliability of interconnections in power electronic devices. While the approach proved a reliable tool for investigating the potential of improvement for alternative interconnect technologies and rejecting design flaws, precise estimations about lifetime in the field are still challenging. Many questions are still in discussion, such as ultra-high cycle fatigue, applicability of Miner's rule, or the influence of on-time and cross-effects with mechanical shocks or humidity. This leaves application engineers with a blurred safety margin. In the following basic considerations of power cycling are described. The introduction shows two applications with different load profiles. Section 2 explains methods of temperature measurement. In Section 3 theoretical requirements for measurement accuracy are given, the obstacle minimal measurement delay and possible workarounds are evaluated. Finally aging effects and their acceleration in different devices are discussed in Section 4. In the conclusion suggestions for power cycling methods and a revision of the end-of-life criteria are made.     

微波半导体器件失效物理述评

本文主要论述用于通信、雷达等电子系统中微波半导体器件的常见失效模式,并分析其主要失效机理。为使器件达到高可靠水平,提出可靠性设计的相应对策。     

Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.     

An efficient reliability testing method combined with thermal performance monitoring

Die attach delamination in power electronic devices is a common failure mode besides bond wire damage. This paper describes the chip and packaging level effects of a newly developed power cycling test on novel mid-power automotive MOSFETs. The introduced method was pilot tested with our new approach, using a recently developed test environment. The idea was to combine the existent guidelines of the most relevant semiconductor characterization and cycling standards while saving time and resources during testing. Thermal transient measurements during the actively mimicked temperature cycling reliability test were evaluated along with K-factor calibration to identify different failure modes. This approach allows distinguishing between electrical and thermal related structural failure modes. The major target was to test the reliability of a new thermal interface material which was used in the MOSFETs under test. We found that the new material was able to withstand the 150 °C temperature amplitude beyond 100,000 cycles without critical failures. The changes of the thermal performance of the complete assembly were tracked from the pre-stress state until a sample reached critical condition.     

真空电子器件工作和非工作可靠性的探讨

论述了几个军用真空电子器件在不同应用条件下的工作和非工作的可靠性情况 ,提出器件在非工作贮存期内的预计失效率模型 ,并讨论在长期非工作贮存期内出现的失效机理及定性得出存放寿命与时间相关的结论。     

Comparison of power cycling reliability of flexible PCB interconnect smaller/thinner and larger/thicker power devices with topside Sn-3.5Ag solder joints

The power cycling reliability of flexible printed circuit board (PCB) interconnect smaller/thinner (ST) 9.5 mm × 5.5 mm × 0.07 mm and larger/thicker (LT) 13.5 mm × 13.5 mm × 0.5 mm single Si diode samples have been studied. With the assumption of creep strain accumulation-induced fatigue cracking as the failure mechanism of the Sn-3.5Ag solder joints, finite element (FE) simulations predicted a higher power cycling reliability of soldering the flexible PCB on a ST Si diode than on a LT Si diode under similar power cycling conditions. Then the power cycling test results of 10 samples for each type are reported and discussed. The samples were constructed with commercially available ST Si diodes with 3.2/0.5/0.3 μm thick AlSiCu/NiP/Pd topside metallization and LT Si diodes with 5/0.1/1/1 μm thick Al/Ti/Ni/Ag topside metallization. In contradiction with the FE prediction, most ST Si diode samples were less reliable than those LT Si diode samples. This can be attributed to the fact that the failure of the ST diode samples was associated with the weak bonding and hence the shear-induced local delamination of the topside solder joints from the AlSiCu metallization, while the failure of the LT diode samples was mainly caused by the creep strain accumulation-induced fatigue cracking within the solder joints. Such results can be used to not only provide better understanding of the different failure mechanisms, but also demonstrate the importance of employing an appropriate topside metallization on the power devices.