K波段单片功率放大器

报道了Ｋ波段的ＰＨＥＭＴ ＭＭＩＣ的设计与研制。ＰＨＥＭＴ器件采用０．５μｍ栅长的３ｉｎｃｈ ＧａＡｓ标准工艺制作。三级的ＭＭＩＣ放大器在１８ＧＨｚ处,线性增益１７ｄＢ,输出功率Ｐ－１＝１９ｄＢｍ。Y     

0.1-0.3μmX射线光刻技术在GaAs器件制作中的应用

对同步辐射Ｘ射线光刻及在ＧａＡｓ ＰＨＥＭＴ器件制作中的应用进行了研究,并制作出栅长０．１５μｍ的ＡｌＧａＡｓ／ＩｎＧａＡｓ／ＧａＡｓ ＰＨＥＭＴ晶体管。研究结果表明,Ｘ射线光刻在肃离图形册结构制作工艺中具有极好的光刻图形质量,在混合光刻工艺中,抑止ＧａＡｓ合金点的形成是取得良好的对准标记的关键。     

单电源低电压InGaP/InGaAsPHEMT低噪声单片放大器

制备了增强型ＩｎＧａＰ／ＩｎＧａＡｓ ＰＨＥＭＴ器件结构、阈值控制以及单电源低电压低噪声单片放大器。获得了阈值电压接近０Ｖ的增强型ＩｎＧａＰ／ＩｎＧａＡｓ ＰＨＥＭＴ器件,并在此基础上设计制作了可在１．５￣３Ｖ低电压和单电源下工作的２．５ＧＨｚ低噪声单片放大器。同时对该电路性能的进一步提高进行了模拟分析。     

深亚微米栅HFET器件工艺研究

通过电子束和接触式曝光相结合的混合曝光方法,并利用复合胶结构,一次电子束曝光制作出具有Ｔ型栅的ＨＦＥＴ（Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）器件,并对０．１μｍ栅长ＨＦＥＴ器件的整套工艺及器件性能进行了研究。形成了一整套具有新特点的ＨＦＥＴ器件制作工艺,获得了良好的器件性能（ｆｔ＝７８ＧＨｚ;ｇｍ＝４４０ｍｓ／ｍｍ）。     

电子束蒸镀半导体发光二极管的减反射膜

用电子束蒸发设备，制备了用于光纤通信等中的ＧａＡｓ和ＩｎＰ系列双异质结红外发光二级管的减反射介质膜。测量结果表明，对发光波长为０．８５μｍ和０．９０μｍ的ＧａＡｌＡｓ／ＧａＡｓ发光二级管，蒸镀四分之一波长厚的Ａｌ２Ｏ３减反射膜，输出光功率在５０ｍＡ和１００ｍＡ电流注入下，可增加２５￣３５％，最大可增加５０％。但对于１．３μｍ波长的ＩｎＧａＡｓＰ／ＩｎＰ型红外发光二极管，用ＺｒＯ２作减反射膜，比用Ａ     

国产金属有机化合物TMGa,TMAl,TMIn和TMSb的MOVPE鉴定

利用我们研制的常压ＭＯＶＰＥ设备对国产ＴＭＧａ、ＴＭＡｌ、ＴＭＩｎ和ＴＭＳｂ进行了鉴定，为此分别生长了ＧａＡｓ、ＡｌＧａＡｓ、ＩｎＰ、ＧａＳｂ外延层和ＧａＡｓ／ＡｌＡｓ、ＧａＳｂ／ＩｎＧａＳｂ超晶格和ＧａＡｓ／ＡｌＧａＡｓ量子阱结构。表征材料纯度的７７Ｋ载流予迁移率分别达到ＧａＡｓ：μ＿ｎ＝５６６００ｃｍ￣２／Ｖ·ｓ，Ａｌ＿（０．２５）Ｇａ＿（０．７５）Ａｓ：μ＿ｎ＝５１６０ｃｍ￣２／Ｖ·ｓ，ＩｎＰ：μ＿ｎ＝６５３００ｃｍ￣２／Ｖ·ｓ，ＧａＳｂ：μ＿ｐ＝５０７６ｃｍ￣２／Ｖ·ｓ。由１０个周期的ＧａＡｓ／ＡｌＡｓ超晶格结构组成的可见光区布拉格反射器已观测到很好的反射光谱和双晶Ｘ射线回摆曲线上高达±２０级的卫星峰。ＧａＡｓ／Ａｌ＿（０．３５）Ｇａ＿（０．６５）Ａｓ量子阱最小阱宽为１０，在ｌｉＫ下由量子尺寸效应导致的光致发光峰能量移动为３９０ｍｅＶ，其线宽为１２ｍｅＶ。这些结果表明上述金属有机化合物已达到较高质量。     

电子束蒸镀半导体光电器件的增透膜

用自动电子束蒸发设备，蒸镀用于光纤通信等中的ＧａＡｓ和ＩｎＰ系列双异质结红外发光二极管的增透膜。结果表明，对波长为０．８μｍ左右的ＧａＡｌＡｓ／ＧａＡｓ发光二极管，蒸镀四分之一波长厚的Ａｌ２Ｏ３介质膜后，其输出光功率在５０ｍＡ和１００ｍＡ电流注入，可增加２５－３５％，最大可增加－５０％。对１．３μｍ波长的ＩｎＰ系列红餐发光管，用ＺｒＯ２作介质增透膜效果更好。     

微波GaAs金属－半导体场效应管可靠性研究的进展

综述了近年来微波ＧａＡｓＭＥＳＦＥＴ可靠性的研究进展。重点介绍了影响其可靠性的因素如栅肖特基结和源／漏欧姆结的相互扩散及表面效应等。     

微波GaAs金属一半导体场效应管可靠性研究的进展

综述了近年来微波ＧａＡｓＭＥＳＦＥＴ可靠性的研究进展。重点介绍了影响其可靠性的因素如栅肖待基结和源／漏欧姆结的相互扩散及表面效应等。     

GaAs功率场效应管失效中源一漏烧毁现象的SEM／SAM研究

采用光学显微镜、扫描电子显微镜（ＳＥＭ）及扫描俄歇微探针（ＳＡＭ）等表面分析技术对ＧａＡｓ功率场效应管（ＦＥＴ）源－漏烧毁失效现象进行了分析研究。ＳＥＭ分析结果表明，源－漏烧毁失效的表面形貌状况较为复杂，烧伤区域的表面形态不尽一致。有源极烧毁较为严重的情况，也有漏极烧伤较严重的情况。ＳＡＭ分析结果说明，源－漏烧毁ＦＥＴ中烧毁处附近的外表完好的源、漏条Ａｕ薄膜下欧姆接触金属薄膜层已完全消失，烧毁源、漏条部位表面化学元素有Ｃ、Ｏ、Ｔｉ、Ｎ和Ｇａ，其中Ｃ、Ｏ在表层几十纳米深度内均有相当高的含量。结合分析结果，讨论了源－漏烧毁的物理机理。     

5 Gb/s单片集成光接收机前端模拟仿真及研制

基于0．5μm GaAs PHEMT标准工艺研制了850nm单片集成光接收机前端,集成方式为PIN光探测器和跨阻放大器。论文依据已发表的文献数据为基础并借助SILVACO公司的模拟软件建立探测器模型,实验结果表明,模型和实测结果对比有较好的一致性。光接收机最高工作速率5Gb／s,其中,探测器光敏面直径50μm,电容0．51pF,暗电流小于30nA。跨阻放大器-3dB带宽接近10GHz,跨阻增益约43dBΩ,最小等效输入噪声电流密度约为17．6pA／Hz^1/2。     

Simulation based performance comparison of transistors designed using standard photolithographic and coarse printing design specifications

In this work a simulation based comparative study of organic field effect transistors designed using standard lithographic and printing designs is presented. The device simulations were performed using two-dimensional drift-diffusion equations with a Poole-Frenkel field dependent mobility model. Both photolithographic and coarse printing transistor designs employed common materials such as 150 nm thick pentacene, 150 nm thick parylene gate insulator, gold source-drain electrodes and aluminum gate electrodes. The major differences between the two fabrication specifications are the minimum source/drain line width and the transistor channel length. The typical specifications for the minimum line width and channel length were 2 μm and 5 μm for photolithography and 25 μm and 20 μm for coarse printing techniques, respectively. The gate, source, and drain capacitances and channel on-resistances at various channel lengths and gate overlaps have been extracted and presented specifically for both process schemes. Due to increased channel length and gate-source/drain overlap of printed electrodes relative to lithographic design, the resulting on-resistance and capacitances for coarse printing are significantly higher. These results demonstrate a substantial operating frequency reduction for printing design relative to photolithographic design. For the tested materials and designs it is shown that the cut-off frequency for the photolithographic process was 400 kHz but decreased to a much lower 26 kHz for the coarse printing process. Since printing technology uses various other materials, which typically have less performance than the ones used for this simulation, the actual printed device might have even lower performance than predicted here.     

Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Contact resistance variation in top-contact organic thin-film transistors with the deposition rate of Au source/drain electrodes

We investigated the effect of the deposition rate of Au source/drain electrodes on the contact resistance of the top-contact organic thin-film transistors (OTFTs). For the formation of source/drain contacts, Au was thermally deposited at the different rates of 0.5, 1.0, 5.0, and 13.0 Å/s. With increasing the Au deposition rate, the contact resistance extracted at the gate voltage of − 30 V could be reduced from 14 × 10⁶ to 2.4 × 10⁶ Ω, resulting in the characteristic improvements of the top-contact OTFT. It is also found that the contact resistance significantly affects the off-state currents of the device having the short channel length of 10 μm. The control of the deposition rate of source/drain electrodes is suggested to optimize the contact properties of the top-contact OTFTs as well as the device performance.     

Silicon-nanowire transistors with intruded nickel-silicide contacts

Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10-30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 10(7). The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 microm, and decreased exponentially for gate lengths exceeding 1 microm.     

Top-gated chemical vapor deposition grown graphene transistors with current saturation

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.     

MOS dosemeter using bismuth oxide (Bi2O3) and copper phthalocyanine (CuPc) polymer thick film

A metal-oxide-silicon (MOS)-capacitor having an Ag/Bi2O3/CuPc/Ag and an MOS-transistor with Ag (gate)-Bi2O3 (gate insulator)-CuPc (semiconductor)-CdO (drain and source) structure were fabricated using screen-printing polymer thick film. The effects of gamma irradiation on the characteristics of both MOS-capacitor and MOS-transistor were investigated. The flat band voltage (VFB) of the MOS-capacitor showed a shift towards the negative gate voltage when exposed to gamma rays. The IDS-VGS characteristics displayed enhancement mode transistor for such devices. The threshold voltage was found to be 4.25 V, which displayed a linear and gradual decrease in DeltaVT = 0.5 V at VDS = 0 V and DeltaVT = 1.0 V at VDS = 2 V when exposed to gamma rays of dose step of 60 Gy.     

Decreasing the role of transverse spatial electron transport and increasing the output power of heterostructure field-effect transistors

We present the first results of development of high-power field-effect transistors (FETs) based on a GaAs heterostructure with quantum well and additional potential barriers optimized to reduce the role of transverse spatial electron transport, which leads to a 1.5-fold increase in the output power. The proposed FETs with a gate length of 0.4?C0.5 ??m and a total gate width of 0.8 mm exhibit a gain above 8 dB at a frequency of 10 GHz, a specific output power above 1.4 W/mm, and an up to 50% power added efficiency.     

Unique carbon-nanotube field-effect transistors with asymmetric source and drain contacts

We have fabricated a type of unique single-walled carbon nanotube field-effect transistor, in which the channel length is only 90 nm and aluminum and gold are used as its drain and source electrodes, respectively. The channel conductance oscillations caused by single-electron tunneling through the asymmetric barriers at the drain and source contacts are observed up to 100 K. Above 100 K, the tunneling fades away, and thermionic emission dominates the conductance at sufficiently negative gate voltages. At room temperature, the device shows diode-like characteristics with a maximum current rectification ratio of approximately 10(4).