A 3.2-V operation single-chip dual-band AlGaAs/GaAs HBT MMIC poweramplifier with active feedback circuit technique

This paper describes the design and experimental results for a 3.2-V operation single-chip AlGaAs/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (IMMIC) power amplifier for GSM900 and DCS1800 dual-band applications. The following two new circuit techniques are proposed for implementing the power amplifier. One is an on-chip HBT bias switch which in turn switches the amplifier between 900 and 1800 MHz. The proposed switch configuration allows the switch using a high turn-on voltage of 1.3 V of AlGaAs/GaAs HBT's to operate with a 3-V low supply voltage, because the switch circuitry needs no stacked configuration. The other is an active feedback circuit (AFB) to prevent permanent failure of HBT's in the output power stage even under severe conditions of oversupply voltage and strongly mismatching load. Experimental results revealed that the proposed feedback circuit, which works as a voltage limiter, can protect the output stage HBT's from an excessive collector voltage swing even when the amplifier is operated under a condition of a 5-V oversupply voltage and a 10:1 voltage standing-wave ratio (VSWR) mismatching load. Under a normal condition of 3.2 V and a 50-Ω matching load, the IC is capable of delivering an output power of 34.5 dBm and a power-added efficiency (PaE) of 52% in a GSM900 mode, and a 32-dBm output power and a 32% PAE in a DCS1800 mode     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

Monolithic RF bandpass track-and-hold

A new bandpass track-and-hold (BP-T/H) open loop architecture is developed as a single stage monolithic circuit with low voltage power supply. The sampling of 912 MHz RF-signal with 100 MS/s is demonstrated by Spectre-Cadence-4.4.6 simulations on 0.35 /spl mu/m RF-SiGe/BiCMOS process of Texas Instruments.     

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

A 10-b 100-Msample/s pipelined subranging analog-digital converter (ADC) has been achieved. Such technologies as a pipelined subranging scheme, a track-and-hold amplifier (THA) with current-switching sampling gates, a 94-dB dc open-loop gain, a 335-MHz unity-gain frequency op amp, and a carry-look-ahead adder for digital error correction are presented. The 3.4-mm×5.6-mm ADC chip was fabricated using a 0.8-μm BiCMOS process and operates with 950-mW power dissipation from a single -5-V power supply     

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-μm BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW     

Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS

The brief presents the design and the implementation of a very-high speed track-and-hold amplifier (THA) for analog-digital converters with high input bandwidth. The THA is based on a half-bridge driving a switched-emitter follower. A lower power consumtpion and a simpler circuit architecture than previously reported bipolar implementations were achieved by means of circuit optimization. In particular, the impact of the aspect ratio of the pMOS current generator in the bridge on the harmonic distortion and on the hold-mode behavior is discussed and modeled. Furthermore, a modification of the cancellation capacitor for feedthrough attenuation, fully compatible with the latest BiCMOS technologies is proposed. The THA was implemented in a 0.8-/spl mu/m SiGe BiSMOS with 30-GHz f/sub T/. It features 10-b resolution at a sampling frequency of 1-GS/s at Nyquist with less than 25 mW of power consumption, from a single 2.7-V power supply.     

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver forwireless applications

A 2.2-V operation, single-chip GaAs MMIC transceiver has been successfully developed for 2.4-GHz-band wireless applications such as wireless local area network terminals. The chip is fabricated using a planar self-aligned gate field-effect transistor. To generate sufficient negative voltage for gate-biasing and to enhance switch power handling capability under a 2.2-V supply, a newly designed negative voltage generator with a voltage doubler (NVG-VD) and a switch control logic circuit are integrated on the chip, together with a power amplifier, a transmit/receive switch, and a low-noise amplifier. The NVG-VD is designed to produce both a 3.3-V positive step-up voltage and a -2.1-V negative voltage under 2.2 V in operation voltage. Biased with these outputs, the logic circuit accommodates high power outputs of over 25 dBm with a low operating voltage of 2.2 V in transmit mode, With a 2.45-GHz modulated signal based on IS-95 standards, a 21-dBm output power and a 33% efficiency are obtained at a ±1.25-MHz-offset adjacent channel power rejection of -45 dBc. In receive mode, a low-noise amplifier achieves a 1.8-dB noise figure and an 11-dB gain with a 3.0-mA current. This transceiver enables significant size and weight reductions in 2.4-GHz-band wireless application terminals     

A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR

We discuss a design technique that makes possible the operation of track-and-hold (T/H) circuits with very low supply voltages, down to 0.5 V. A 0.5-V 1-Msps T/H circuit with a 60-dB SNDR is presented. The fully differential circuit is fabricated in the CMOS part of a 0.25-mum BiCMOS process, with standard 0.6-V V_T devices, and uses true low-voltage design techniques with no clock boosting and no voltage boosting. The T/H circuit has a measured current consumption of 600 muA     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

A 2.7-V 300-MS/s track-and-hold amplifier

A fully differential bipolar track-and-hold amplifier (THA) employs an open-loop linearization technique compatible with low supply voltage. A feedthrough reduction method utilizes the junction capacitance of a replica switch to provide a close match to the junction capacitance of the main switch. The differential full-scale (FS) input range is 0.5 V. In the track mode, with f_in=10 MHz, FS sinewave input, the measured total harmonic distortion (THD) is less than -72 dB. With f_s=300 MS/s and f_in=10-50 MHz, FS sinewave input, the measured THD is less than -65 dB. This THD measurement reflects the held values as well as the tracking components of the output waveform. With f_s<10 MS/s and f_in=10-50 MHz, FS sinewave input, the measured feedthrough is less than -60 dB. The hold capacitance is 2.5 pF and the differential droop rate is 16 mV/μs. The THA consumes 32 mW from a 2.7-V power supply and is fabricated in a 0.5-μm, 18-GHz BiCMOS process     

一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

Programmable switched-capacitor bump equalizer architecture

A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3-μm CMOS (p-well) technology and occupies an area of 3.36 mm², including an additional test amplifier and test buffer. The circuit operating from ±5-V power supplies typically dissipates 60 mW when sampled at 75 kHz     

A wide-band high-voltage monolithic amplifier

A monolithic amplifier capable of 80-V swing and 1.7-V/NS slew rate has been fabricated using standard integrated circuit techniques. The amplifier is intended for capacitive loads such as in electrostatic deflection applications. The totem-pole technique is combined with active feedback to produce this large voltage swing without excessive power consumption. A new output circuit linked with a floating current source is used to supply large accurate positive and negative charging currents over a large dynamic range. The amplifier voltage range is extendable by increasing the degree of stacking in the totem-pole arrangement.     

An 8-b, 40 msamples/s switched-current-mode track-and-hold circuiton a BiCMOS sea-of-gates array

A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm²     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

A monolithic Si PCS-CDMA power amplifier with 30% PAE at 1.9 GHzusing a novel biasing scheme

A monolithic Si personal-communication system-CDMA power amplifier (PA) capable of delivering 28.2-dBm output power with 30% power-added efficiency and -45-dBc adjacent-channel-power ratio at 1.9 GHz and 3.6-V supply voltage is presented for the first time in this paper. The PA implemented in a 30-GHz BiCMOS process incorporates a novel impedance-controllable biasing scheme to control the class of operation and bias impedance of the output stage. Both simulated and measured results are presented for comparison     

A BiCMOS low-distortion 8-MHz low-pass filter

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2-μm 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than ±1 dB over a 100°C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V_pp, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V_pp inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc     

Application of merged current switch logic for a built-in logicblock observer operating at 1 Gbit/s and 1.2 V supply

The authors show that merged current switch logic is an excellent candidate for enabling low supply voltages and maintaining an operating speed in the GHz range. The demonstration circuit fabricated in a 0.8 μm BiCMOS process operates at supply voltages as low as 1.2 V with a bit rate of 1 Gbit/s. The dynamic power consumption is 461 μW/gate     

A wide-band class AB monolithic power amplifier

A class AB Si monolithic power amplifier which achieves DC to 830-MHz small-signal bandwidth and delivers +20 dBm at 1-dB gain compression power and 100 MHz to a 50-Ω load is described. The circuits dissipates 540-mW quiescent power from a 12-V supply and has input and output impedances matched to 50 Ω. The circuit has a small die size, is housed in an inexpensive package, and exhibits excellent tolerance to input overdrive