0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。     

一种带瞬态增强电路的无电容型LDO

设计了一种可用于SOC片内供电的新型瞬态增强无电容型线性压差调整器电路.相对于需要由误差放大器、缓冲器和反馈网络三级结构构成的传统LDO,该设计在简单的一级单管控制结构上增加了摆率增强电路(SRE)来实现瞬态响应增强,可以更容易地进行频率补偿,在简化设计过程的同时,保证了较快的响应速度.     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

基于高摆率误差放大器的无片外电容LDO设计

为了解决无片外电容低压差线性稳压器(LDO)的瞬态响应性能较差的问题,采用跨导提高技术设计了一种高摆率的误差放大器.在误差放大器的基础上,通过电容将LDO的输出端耦合至电流镜构建瞬态增强电路,提升LDO的瞬态响应能力,且瞬态增强电路可以引入两个左半平面零点,改善环路的稳定性.同时,误差放大器采用动态偏置结构,进一步减小...     

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and I_Q of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.     

一种带双向使能的负LDO电路设计

设计了一款带正负双向使能功能的负电压输出的LDO。介绍了LDO的基本工作原理,对比了正、负输出LDO的区别,对双向使能电路结构进行了详细设计。采用Cadence对电路进行直流和瞬态仿真验证,仿真结果表明,该LDO在特定的正负两个使能区间均能完全导通,其开启关断点与电路设计吻合。在设计该双向使能结构的同时,保留了使能电路低功耗的特点。     

用于GaN HEMT栅驱动芯片的快速响应LDO电路

设计了一种用于GaN高电子迁移率晶体管(High-Electron-Mobility Transistor,HEMT)器件栅驱动芯片的快速响应低压差线性稳压器(Low Dropout Regulator,LDO)电路,可为高速变化的数字电路提供快速响应的供电电压。该电路采用动态偏置结构,通过在大负载发生时给误差放大器增加一个额外的动态偏置结构,来加快输出端的瞬态响应速度。基于0.18μm BCD工艺,完成了电路设计验证。仿真结果显示LDO瞬态响应时间小于0.5μs,可满足频率达1 MHz的GaN HEMT器件栅驱动芯片应用要求。     

LDO中动态补偿电路的设计

分析了LDO稳压器的稳定性问题,在此基础上提出了一种新型的动态补偿电路,利用MOS管的开关电阻、寄生电容等构成的电阻电容网络,通过采样负载电流而改变MOS开关管的工作点或工作状态,即改变开关电阻、寄生电容的值,从而实现动态的频率补偿,保证了LDO稳压器的UGF（Unity Frequency）基本不随负载变化,使其在所有负载内均能稳定工作.与传统方法相比,该电路具有恒定的带宽,大大提高了系统的瞬态响应性能,使LDO稳压器具有较高的电压调整率和负载调整率.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces V_OUT offset at medium to heavy load to counteract the V_OUT drop, which is caused by I_LOAD increase. Hence, transient performances of LDO and V_OUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with I_LOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the V_OUT drop between light load and full load reduces to 0.16 mV.     

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6-/spl mu/m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%.     

大电流负载的片上LDO系统设计

 本文分析了传统大电流负载的LDO(Low-dropout Regulator)系统实现系统稳定性和瞬态响应提高的局限性,在此基础上,提出了一种片内集成的瞬态响应提高技术.此技术无需外挂电容和等效串联电阻(Equivalent Series Resistor,ESR),即能使系统在全负载范围内保持稳定性和良好的纹波抑制能力.仿真结果表明,系统空载时,静态电流为64μA,且最大能提供800mA的负载电流,1KHz时的电源抑制比达到-60dB,当负载电流以800mA/5μs跳变时,最大下冲电压为400mV,上冲电压为536mV,恢复时间分别只需6.7μs和12.8μs,版图面积约为0.64mm².     

一种超低静态电流LDO线性稳压器的设计

为了延长便携式、可穿戴医疗设备的待机时间,设计了一种具有超低静态电流的低压差(LDO)线性稳压器。采用误差放大器与基准电路相结合的结构,在降低静态电流的同时减小芯片面积;其次,利用负载检测模块,降低了空载及轻载时过温保护和过流保护等模块的静态电流。采用自适应偏置电流技术来动态调整稳压环路各支路的工作电流以及零点频率补偿方式,解决了静态功耗与瞬态响应和环路带宽间的矛盾。该LDO线性稳压器采用0.35μm CMOS工艺进行流片加工,测试结果表明,该LDO线性稳压器静态电流为700 nA,最大负载电流为150 mA,轻载与满载跳变时上过冲电压为63 mV,下过冲电压为55 mV。     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.     

一种超快速响应的片上线性稳压器

设计了一种片上超高速低压差(LDO,low dropout)线性稳压器。在仅利用100pF输出电容情况下,采用一种新颖的快速响应回路,使LDO可以响应20ns内负载电流由空载到满载的瞬态变化,大大提高了系统的瞬态响应性能。快速响应回路同时具有补偿作用,保证LDO的稳定性。芯片设计基于SMIC公司的0.35μm CMOS工艺信号模型。测试结果表明,LDO在工作模式下的静态电流约为120μA,在等待模式下的静态电流约为9μA,对上升、下降时间均小于60ns的脉冲信号具有良好的瞬态响应。     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18 μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7 μs and the maximum undershoot and overshoot are as low as 55 mV and 30 mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37 mV/V and 2 μV/mA, respectively.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。