数字电路可测性设计的一种故障定位方法

在逻辑函数ReedMuller模式的电路可测性设计方面，文章采用AND门阵列和XOR门树结构来设计电路，提出了一种设计方案，可实现任意逻辑函数的功能，而且所得电路具有通用测试集和完全可故障定位的特点。给出了进行故障定位的方法，并可把它应用于其他相关电路的可测性设计。     

基于谱和函数修改技术的逻辑电路设计

基于谱技术和逻辑函数修改技术 ,本文讨论了逻辑函数的一种优化设计方法 .实例结果表明 ,相对于传统的逻辑函数设计方法 ,它具有电路结构简单 ,成本低的特点     

一种新型组合逻辑分频电路的设计

设计实现一种新型的分频电路,与以往的动态触发寄存器结构不同,采用组合逻辑电路进行分频,尤其对于高阶分频的情况,更占优势,电路门数少、成本低、速度快。以4096分频为例,对比传统与新型电路的优劣,基本达到预期的结果。     

适用于嵌入式应用的高速信号采集电路

介绍了高速采集电路的一个现场数据采集系统的前端．该采集电路由高速A／D,CPLD及高速存储器构成,类似数字示波器或采样卡,具有高速采样,高速缓存以及完整的触发设置功能,适合采集高速瞬时信号．但与通用信号采集产品不同的是该产品具有开放的总线接口．可直接连接各种单片微机,DPS或微处理器,适用于嵌入式系统的应用场合．描述了该电路的功能和原理,重点讨论“Roll Mode”逻辑及其如何实现对高速瞬时信号的捕获功能．     

逻辑代数与常用逻辑门电路

近年来,电子科学和技术取得了飞速发展,其标志就是电子计算机的普及和大规模集成电路的广泛应用,数字逻辑的产品层出不穷,在这种情况下,传统的关于数字电路的内容也随之起了很大的变化,在数字电路领域EDA工具已经相当成熟,无论是电路内部结构设计还是电路系统设计,以前的手工设计都被计算机辅助设计或自动设计所取代.数字电路与数字电子技术广泛的应用于电视、雷达、通信、电子计算机、自动控制、航天等科学技术各个领域,数字逻辑基础涉及数字技术中的基本原理、基本分析和设计方法,具有很强的工程实践性。     

110kV内桥接线防误闭锁逻辑的应用与讨论

内桥接线作为110kV变电所一种典型的接线方式,在长兴局得到普遍的应用,在近年投产的110kV变电所无一例外应用了内桥接线,作为防误操作的关键一环。防误闭锁逻辑的设计与规范也愈来愈被重视,本文详细分析了110kV内桥接线的防误闭锁逻辑,以探讨其在变电所中的规范使用,以期更规范的使用,发挥更好的防误功能。     

基于模糊逻辑专家系统的机车动力系统电力故障诊断

智能控制理论的发展为解决电力驱动系统故障诊断带来了新方法.对于非线性和不确定模型系统而言,智能控制中的模糊逻辑控制和专家系统是有效策略之一.结合两种系统优点,构建模糊逻辑专家系统,对电源电路进行状态监控和故障分析.并通过对典型电源电路的分析,提出一种通用的故障分析系统构架,为今后的相关研究确立了基础.     

多波形显示技术及其扩展

本文提出了在通用示波器上同时显示多路数字信号的方法，并使之扩展成具有逻辑分析仪的功能，为数字电路、数字系统提供了简便的测试手段．     

交通灯控制器的设计及其CPLD实现

EDA技术是用于电子产品设计中比较先进的技术,可以代替设计者完成电子系统设计中的大部分工作,而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持,既缩短了研发周期,又大大节约了成本,受到了电子工程师的青睐。在设计中采用EDA技术,通过广泛应用的VHDL硬件电路描述语言,实现交通灯系统控制器的设计,利用MAXPLUSⅡ集成开发环境进行综合、仿真,并下载到CPLD可编程逻辑器件中,完成系统的控制任务。     

频率/待测量变换的GAL、ERROM设计方法

本文提出了以通用阵列逻辑器件 GAL 和只读存贮器 EPROM 为核心器件的频率/待测量变换的设计方法。配以数字式传感器及用最小二乘法编制的曲线自动分段拟合程序生成的 EPROM 中的数据,可用于力、温度、光强等非电量的测量显示和控制。这种装置与采用微处理器的电路相比,有相同的测量精度,电路简单,而且保密性好.     

大气采样器稳流技术的设计

介绍了应用可编程逻辑控制器（PLC）和差压传感器构建稳流采样系统实现大气采样器采样流量恒定的设计原理和应用。     

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Accurate and computer efficient modelling of single event transients in CMOS circuits

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate     

Advances in the modeling of single electron transistors for the design of integrated circuit

Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.     

一种SETMOS二阶带通滤波器设计实现

单电子晶体管（SET）作为一种纳电子器件有着较大的优势,将SET与纳米MOS混合构成的器件（SETMOS）是目前研究的热点之一。SETMOS作为一种新的混合器件,在结合了两者优点的同时,具有与SET一样的库仑振荡特性和MOS高增益等特性。文章基于一种sETM0s混合结构的电压电流特性的数学模型,设计并实现了一种SETMOS二阶带通滤波器,阐述了这种SETMOS带通滤波器的结构、工作条件、性能、参数和特点,并用PSpice对其传输特性进行了仿真验证,结果证明,SETMOS在其通带范围内具有良好的带通幅频特性,且具有低电压、低功耗和高频的特点。     

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “ quantization threshold”) that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studied for the current-biased negative differential resistance (NDR) circuit and hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.      

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

All-optical photonic crystal AND,XOR, and OR logic gates using nonlinear Kerr effect and ring resonators

In this article, two structures are proposed for all-optical AND, XOR, and OR logic gates based on nonlinear photonic crystals. The proposed structures include a Y-junction and ring resonator-based limiters. Two different structures are designed as the limiter in order to produce AND–XOR and AND–OR logic gates. Nonlinear rods of proposed structure have been used in order to create the frequency shift for different values of input power. Finite difference time domain method has been utilized to simulate the performance of proposed logic gates. Simulation results show that the smallest ON–OFF logic-level contrast ratio for the structures proposed for AND–XOR and AND–OR logic gates are 20.29 dB and 16.7 dB, respectively.     

All-optical logic gates based on photoinduced anisotropy of bacteriorhodopsin film

All-optical logic gates based on photoinduced anisotropy of bacteriorhodopsin (BR) film are proposed. The photoinduced anisotropy in BR film, which arises from the selective absorption of BR molecules to polarized light, can be controlled by changing the amplitudes and polarizations of exiting beams. As a consequence, the polarization of the probe light passing through the BR film can be controlled by the polarization of the exiting beam. Based on this property, a novel scheme of all-optical logic gates, such as AND, OR, XOR and NOT, has been implemented via the pump-probe technique. A theoretical model for the all-optical logic gates is proposed, and the theoretical predictions are demonstrated with the experimental results.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.