双阈值CMOS电路静态功耗优化

集成电路设计进入深亚微米阶段后，静态功能不容忽视，提出一种基于双阈值电压的静态功耗优化算法，利用ISCAS85和ISCAS89电路集的实验结果表明，20％以上的静态功耗可以被消除（大规模电路在90％以上）。同时，文中算法也从很大程度上减小了电路的竞争冒险，提高了电路的性能。     

一个面向低功耗设计的RFID系统研究与实现

功耗问题制约着射频识别（RFID）系统的应用领域，论文依据射频识别系统特点和工作原理，在读写器端将硬件结构级和软件级功耗优化相结合，在完成射频识别、存储器管理、时钟控制和通信接口的基础上，对待机和射频读写时采用不同的功耗策略，设计实现了一种面向低功耗设计的射频识别系统，最后对功耗情况进行了实验比较和分析，测试结果表明该系统完全达到低功耗应用要求，并且已经在澳门海关得到了成功运用。     

一种低功耗可重构Cache的重构算法

随着半导体技术的发展,芯片上的功率密度也逐渐增大,这使得功耗问题在芯片设计时越来越受到人们的关注.片上Cache是处理器芯片中的主要功耗源之一,采用低功耗Cache可有效降低处理器整体功耗.对低功耗Cache设计进行了研究.介绍了当前低功耗Cache设计的主要方法和一种低功耗可重构的数据Cache的体系结构及相应的重构算法.给出了一种新的重构算法——LoW-High Boundary（LHB）算法.实验表明LHB算法在性能和功耗上均优于原算法.     

基于遗传算法的最大开启电流估计

集成电路设计进入深亚微米阶段后，静态功耗成为低功耗设计中的一个瓶颈．电源门控法可以同时有效地降低动态功耗和静态功耗，是一项具有广阔应用前景的技术．电源门控电路的最大电流是由最大开启电流和最大的正常运行电流决定，它是电路设计的一个十分重要的参数，如何对它进行快速准确的估计已经成为一个新的问题．另外，冒险功耗是电路整体功耗中非常重要的组成部分，该文通过研究发现，在电路开启阶段同样存在冒险，同时消耗了大量的能量．文章考虑了组合电路的冒险现象，提出了一种基于遗传算法的最大开启电流的估计方法，对ISCAS85电路的实验结果表明，电源门控电路的开启最大功耗可能比正常情况下的最大功耗还要大．该文的方法具有较小的复杂性，可以仅用随机模拟的2．77％的时间，获得12．90％的最大开启电流值增量。     

一种高效率低功耗的电荷泵设计

在集成电路设计中,随着工艺尺寸越来越小,电路在功耗方面的要求越来越高。设计高效率低功耗的电荷泵（charge pump）,可以提高电荷泵的工作效率,降低整个电路的功耗。这里介绍了一种高效率低功耗的电荷泵,通过仿真图像可以清楚地看到电荷泵的工作情况,看到它是如何实现高效率低功耗的。     

应用输入向量控制技术降低漏电功耗的快速算法

随着工艺的发展,为保证电路的性能和噪声容限必须降低阈值电压,这将导致漏电流呈指数增长,漏电功耗因而将逐渐超过动态功耗占据主导地位.CMOS的堆栈效应导致电路在不同向量下的静态功耗不同,因此在电路进入睡眠状态时使用输入向量控制技术是一种低功耗设计的有效方法,如何快速找到一个可降低电路漏电功耗的向量就成了问题的关键.介绍了一种在给定向量集合中查找低功耗向量的快速算法--基于概率传递的标记算法,并为此开发了一个事件驱动的门级组合电路仿真器.通过对ISCAS和龙芯处理器电路的实验结果表明,该算法同传统方法比较可以提高性能3.4倍,误差率仅约0.14%.     

VLSI的门级低功耗设计优化技术

低功耗设计已成为微电子领域的难点和热点。由于门级低功耗设计可以得到较好的精度和效率而被广泛的研究和应用。低功耗设计包括功耗估算和功耗优化。本文基于CMOS功耗计算模型 ,对各种门级低功耗设计方法进行了阐述和分析。     

中小尺寸液晶屏图形显示控制芯片的低功耗设计

在VLSI设计中，低功耗的要求已经变得越来越重要。低功耗设计可以在不同的设计层次考虑．采用低功耗技术的层次越高，对功耗的改善越显著。本文针对一款中小尺寸液晶屏图形显示控制芯片的设计，提出了一种有效的低功耗设计方案。通过功耗分析比较表明．该设计方案极大的改善了这款芯片的功耗特性。     

Cadence混合信号低功耗设计流程助力SiliconLabs降低MCU功耗

Cadence设计系统公司宣布,SiliconLabs采用完整的Cadence混合信号低功耗设计流程,使其最新款节能型基于ARM微控制器（MCU）的功耗大幅降低。搭载了ARMCortex—M4核心的新款EFM32WonderGecko,功耗显著降低,即使运行在更高的温度,也能延长电池使用时间。这款微控制器瞄准对功耗敏感的应用场合,例如智能能源和自动化领域,无论在活动还是在睡眠模式下均可实现低功耗运行。     

基于Innovus的低功耗物理设计

为了减少芯片功耗,可靠的低功耗物理设计必不可少。基于新一代布局布线工具Innovus,分四个部分阐述了新的低功耗物理设计流程。这些内容包括:基于低功耗的物理库设计;低功耗布局和优化、基于输入向量的功耗优化;低功耗时钟树协同设计CCOPT(clock concurrent optimization);时钟树后低功耗优化。Innovus作为Cadence全新的布局布线工具,提供基于Giga Opt引擎的功耗驱动优化和高级时钟树协同优化(CCOPT)等方法,有效帮助设计者实现低功耗芯片设计。全新的低功耗物理设计可改善芯片数字逻辑15%功耗。     

基于转换概率及RO结构的硬件木马检测

针对硬件木马倾向于在电路低转换概率节点插入的问题,提出了一种在这些节点处构建环形振荡器（RO）结构的方法来检测硬件木马。该方法首先计算电路节点的转换概率并挑选出低于转换概率阈值的节点,然后在挑选出的节点处构建RO结构,通过RO延时的变化进行木马的检测。实验以ISCAS’85基准电路为基础,并在Spartan6 FPGA开发板实现。实验结果表明,在可接受的面积和功耗开销下,可以检测到仅有一到两个门的小型木马电路,弥补了旁路信号分析法检测小型木马的不足。     

面向功耗优化的CMOL电路容错映射

针对CMOS/纳米线/分子混合(CMOL)电路的缺陷导致电路功耗增加这一问题,提出基于单元限用的容错映射方法.首先建立缺陷对的功耗模型,分析常连缺陷对的映射模式对功耗的影响;然后通过高功耗单元的限用与功耗约束的设置,以减少高成本映射模式带来的功耗开销;最后采用改进的遗传算法完成电路容错映射. ISCAS标准测试电路的实验结果表明,所提方法在成功容错映射的基础上,有效地减少了电路的功耗与面积,同时对求解速度也有较好的优化.     

An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations

With shrinking technology, the increase in variability of process, voltage, and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However, neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally, the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.     

基于复平面圆图的RFID振荡器设计方法研究

为降低RFID射频振荡器功耗并缩小其体积,提出了一种改善其性能的设计方法。采用晶体管和无源网络产生振荡,分析了单项参数的变化规律,给出了提高综合性能的方法以及射频振荡器的电路结构。仿真结果表明,晶体管稳定性对振荡器的设计有一定影响,配以正反馈可增加不稳定性,振荡器起振越快,功率输出越大,综合利用史密斯圆图和复平面上的稳定性边界可有效分配性能指标,为改善射频振荡器的性能开辟了一种新的途径。     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.     

A novel hybrid gravitational search and pattern search algorithm for load frequency control of nonlinear power system

In this paper, a hybrid gravitational search algorithm (GSA) and pattern search (PS) technique is proposed for load frequency control (LFC) of multi-area power system. Initially, various conventional error criterions are considered, the PI controller parameters for a two-area power system are optimized employing GSA and the effect of objective function on system performance is analyzed. Then GSA control parameters are tuned by carrying out multiple runs of algorithm for each control parameter variation. After that PS is employed to fine tune the best solution provided by GSA. Further, modifications in the objective function and controller structure are introduced and the controller parameters are optimized employing the proposed hybrid GSA and PS (hGSA-PS) approach. The superiority of the proposed approach is demonstrated by comparing the results with some recently published modern heuristic optimization techniques such as firefly algorithm (FA), differential evolution (DE), bacteria foraging optimization algorithm (BFOA), particle swarm optimization (PSO), hybrid BFOA-PSO, NSGA-II and genetic algorithm (GA) for the same interconnected power system. Additionally, sensitivity analysis is performed by varying the system parameters and operating load conditions from their nominal values. Also, the proposed approach is extended to two-area reheat thermal power system by considering the physical constraints such as reheat turbine, generation rate constraint (GRC) and governor dead band (GDB) nonlinearity. Finally, to demonstrate the ability of the proposed algorithm to cope with nonlinear and unequal interconnected areas with different controller coefficients, the study is extended to a nonlinear three unequal area power system and the controller parameters of each area are optimized using proposed hGSA-PS technique.     

Faster power estimation of CMOS designs using vector compaction - a fractal approach

Low power digital complementary metal oxide semiconductor (CMOS) circuit design requires accurate power estimation. In this paper, we present a compaction algorithm for generating compact vector sets to estimate power efficiently. Power can be estimated using dynamic (simulation) or static (statistical/probabilistic) techniques. Dynamic power estimation techniques simulate the design using a large input vector set for accurate estimation. However, the simulation time is prohibitively long for bigger designs with larger vector sets. The statistical methods, on the other hand, use analytical tools that make them faster but less accurate. To achieve the accuracy of dynamic power estimation and the speed of statistical methods, one approach is to generate a compact, representative vector set that has the same switching transition behavior as the original larger vector set. The compaction algorithm presented in this paper uses fractal concepts to generate such a compact vector set. The fractal technique quantifies correlation by a fractal parameter which can be determined faster than calculating correlation explicitly. Experimental results on circuits from the ISCAS85 and ISCAS89 benchmark suites, with correlated input vector sets, resulted in a maximum compaction ratio of 65.57X (average 38.14X) and maximum power estimation error of 2.4% (average 2.06%). Since the size of the compact vector set used for simulation is smaller, the simulation time will be shorter and will significantly speed up the design cycle.     

基于跟踪微分器的基波测量方法研究

电网基波参数特别是基波频率在谐波分析与治理中具有重要的地位,也是电能质量、电能计量以及电力系统控制等领域的重要技术指标。在非同步采样情况下,针对基于频域法测量基波频率存在频谱泄露现象和测算精度不高的问题,提出了基于跟踪微分器(Tracking Differentiator,TD)的基波参数时域测量方法。该方法的主要思想是将检测到的基波信号通过TD来获取基波跟踪信号及其微分跟踪信号,再通过这两个信号的最大幅值即可获取基波的幅值、频率和初相位参数。仿真结果表明,本文方法只需要60%额定工频周期窗口的样本数据即可获得较高精度的基波参数测算值,是一种有效的基波参数测量方法。