一种采用饱和区MOS管作调节开关的电荷泵

为了得到稳定的输出电压,电荷泵电路需要通过负反馈系统进行控制.在传统的"Skip"模式电荷泵中,采用工作在线性区的MOS管做开关,通过控制振荡器来调节输出电压,但这种方式会产生较大的输出电压纹波.设计了一种采用饱和区MOS管作调节开关的电荷泵,通过控制饱和区MOS管的导通电阻来调节电荷泵的输出电压.它工作在占空比为50%的方波信号下,具有很低的输出电压纹波(37mV).     

基于DVS的多核实时系统节能调度

动态电压调节是一种有效的节能技术．本文提出了多核处理器平台上的一种近似最优的动态电压调节算法．算法将电压调节问题转化为松弛时间分配问题，由任务集结构找到存在的松弛时间，针对不同类型的松弛时间，使用了并行补偿等分配方法．实验结果表明本文的算法能够有效的降低能量消耗且具有较低的时间复杂度．     

基于电压灵敏度矩阵的分布式配电网电压控制

随着我国分布式光伏的大规模发展,配电网电压的控制变得越来越重要。为了提高配电网中分布式光伏发电的负载能力,文中提出了一种基于电压灵敏度矩阵的配电网电压控制方法。该方法首先通过分析节点注入功率变化对节点电压的影响,构建关联各主节点有功功率和无功功率的电压灵敏度矩阵。然后依据电压灵敏度矩阵,充分利用分布式光伏逆变器的无功调节能力,将配电网的节点电压快速控制在工作范围之内。仿真结果表明,该方法可以有效降低分布式配电网在各种工作场景下的电压偏差,提高电压质量。     

东芝稳压集成电路TA58LTOOF

<正> TA58LT00F 是东芝公司推出的一种正电压输出的五引脚稳压集成电路,具有输出通/断控制功能(输出通/断控制端V_(EN)高电平通,低电平断),通过改变其电压调节引脚 V_(ADJ)的电压,输出电压可在2.5V～13.4V 之间变化,其最大输出电流为1 50mA。TA58LT00F 还具有待机电流小(只有1μA),过压、过流、过热、输入电源电压正、负极性接反和60V 瞬间过压保护功能。它采用了 HSIP5-P-1.27B 封     

飞机配电系统容错技术的设计研究

为了提升电力飞机配电系统电压供应品质,本论文利用重构控制理论来设计电压调节器用以有效的达到电压调节的目的。利用Dobson和Chiang提出的电力系统模型并假设在配电系统中电容器与变压器为有效的控制输入,在本论文提出了电压调节器设计准则。更进一步我们以容错控制的观念来设计主动式及被动式容错控制律,使得飞机配电系统在控制器发生故障或异常情况时,依然可以达到电压调节的目的。     

无直流电压传感器的单相APFC变换器

文章对一种只检测交流输入电压而不需要检测输出直流电压的简化单相PFC变换器进行了理论分析和研究。在构建控制电路时,不需要常规PFC变换器中的输出电压传感器和输入电流传感器。PFC变换器的主电路为整流电路的直流侧接一级Boost电路。在控制电路中,使用电感L、等效负载电阻Rd等电路参数产生正弦电流波形基准,输出电压直接由控制量Kd(=Ed/Ea)来调节。通过控制,可以得到恒定的直流输出电压和与交流输入电压同相位的正弦电流波形。仿真结果证明了该变换器的可行性。     

东芝稳压集成电路TA58LT00F

TA58LT00F是东芝公司推出的一种正电压输出的五引脚稳压集成电路,具有输出通／断控制功能（输出通／断控制端VBN高电平通,低电平断）,通过改变其电压调节引脚VAQJ的电压,     

基于功耗大小的DVS频率选择策略

动态电压调节技术（DynamicVoltageScaling,DVS）是一种有效的运用于实时嵌入式系统中的低功耗技术。动态电源管理（DynamicPowerManagement,DPM）是一种通过选择性关闭处于欠负载状态的模块,使系统功耗最小化的策略。实时嵌入式系统中DVS技术不仅要实现系统功耗的降低,同时也要兼顾系统的实时性。但是,单纯的DVS技术或是DPM技术都不能完全解决实时嵌入式系统中的功耗问题。文章针对已有的动态电压调节策略,分析DPM策略在动态电压调节过程中对系统总功耗的影响,从而提出基于功耗大小的DVS控制策略。     

实用数控数显直流稳压电源

直流稳压电源是最常用的电子仪器,根据对输出电压的调节与指示方式不同主要分有两类。第一类最常用的是采用电位器调节输出电压并通过机械电压表头指示输出电压值,这一类直流稳压电源存在由于电位器机械磨损而容易出现输出电压变化、调节困难以及电压指示精度较低等缺点。第二类采用单片机控制输出电压调节与电压显示,这类直流稳压电源虽然解决了第一类直流稳压电源存在的缺点,但存在需要单片机开发工具且制作与调试较困难等缺点。     

基于无线传感器网络能耗系统的研究

节能已经成为无线传感器网络研究的核心部分。该文研究了无线传感器网络拓扑结构的邻近节点数对网络能耗的影响,主要采用动态电压调节技术(DVS)来降低无线传感器网络中节点的能耗。动态电压调节主要通过减少门等效电容、供电电压以及降低转换因子、时钟频率来达到降低动态能耗的目的,其中,降低供电电压节能效果最佳。与其他方法相比,动态电压调节降低能耗更加明显、效率更高。通过在CC2430节点芯片上测试验证,通过改变其分频比,得出了功耗和频率的近似线性关系。     

基于DVFS的移动通信终端省电方案

本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间.     

动态电压调整多处理器实时系统任务调度

动态电压调整DVS（Dynamic Voltage Scaling）是根据处理器电压（速度）降低之后，能量消耗平方级的减少这一原理提出的。文章通过DVS机制在多处理器实时系统中进行任务调度．通过对任务调度中的静态能量管理进行分析，在此基础上提出了一种新的基于DVS的适用于多处理器实时系统中的调度算法。这种新的调度算法是通过对贪婪法调度进行研究，发现其不足．并以此为基础进行改进。结合了动态电压调整的多处理器实时系统任务调度的能量消耗比普通的任务调度能量消耗有了很大的改善。     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

A survey and measurement study of GPU DVFS on energy conservation

Energy efficiency has become one of the top design criteria for current computing systems. The dynamic voltage and frequency scaling (DVFS) has been widely adopted by laptop computers, servers, and mobile devices to conserve energy, while the GPU DVFS is still at a certain early age. This paper aims at exploring the impact of GPU DVFS on the application performance and power consumption, and furthermore, on energy conservation. We survey the state-of-the-art GPU DVFS characterizations, and then summarize recent research works on GPU power and performance models. We also conduct real GPU DVFS experiments on NVIDIA Fermi and Maxwell GPUs. According to our experimental results, GPU DVFS has significant potential for energy saving. The effect of scaling core voltage/frequency and memory voltage/frequency depends on not only the GPU architectures, but also the characteristic of GPU applications.     

芯片功耗限制对器件按比例缩小的影响

随着器件特征尺寸的不断缩小，电路功耗限制将对器件的进一步按比例缩小产生显著影响。文章在一些假设的前提下提出一简单物理模型对这一影响进行建模，并据此模型对开启电压变化时的影响作了分析。文中还对功耗管理和低温工作的作用进行了探讨。     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high-k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high-k 45 nm.     

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip (SoC). Dynamic voltage scaling (DVS) is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 m technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.     

Dynamic voltage scaling for series hybrid amplifiers

We present an optimization of the voltage scaling algorithm in low power audio class-G amplifier for headphones application to allow longer playback time. The optimization approach minimizes the voltage difference between the internal audio amplifier power supply and its output signal over a large range of operating conditions. The modeling is based on a behavioral model enabling accurate and rapid evaluation of efficiency and audio quality with realistic input stimuli. The model validated in practice is used to optimize the voltage scaling using only few power supply levels. Thanks to a global search algorithm followed by a local one, the optimization gives the better parameters for voltage scaling algorithm while keeping a good audio quality. The proposed configuration increases the efficiency up to 48% at nominal operation.     

Automatic Performance Setting for Dynamic Voltage Scaling

The emphasis on processors that are both low power and high performance has resulted in the incorporation of dynamic voltage scaling into processor designs. This feature allows one to make fine granularity tradeoffs between power use and performance, provided there is a mechanism in the OS to control that tradeoff. In this paper, we describe a novel software approach to automatically controlling dynamic voltage scaling in order to optimize energy use. Our mechanism is implemented in the Linux kernel and requires no modification of user programs. Unlike previous automated approaches, our method works equally well with irregular and multiprogrammed workloads. Moreover, it has the ability to ensure that the quality of interactive performance is within user specified parameters. Our experiments show that as a result of our algorithm, processor energy savings of as much as 75% can be achieved with only a minimal impact on the user experience.