Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.Kye-Shin Lee received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1992 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas.He was with LG Semicon Co. (now Hynix Semicon Inc.), Seoul, Korea from 1994 to 1999, where he was involved in mixed signal circuit design and testing of BW/Color CCD chipsets including timing/sync. signal generator, camera signal processor, USB camera interface, and sigma-delta CODECs for audio and voice band applications. His research has been focused on switched-capacitor circuits, sigma-delta modulators, and pipeline ADCs.Yunyoung Choi received the B.S. degree from Kwangwoon University, Seoul, Korea, in 1999 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas. He worked for Texas Instruments, Dallas, from May to December 2003 at the Wireless Business Unit. His research interest includes sigma-delta A/D and D/A converters for audio systems and RF applications.Franco Maloberti received the Laurea Degree in physics (summa cum laude) from the University of Parma, Parma, Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico, in 1996.In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group, University of Pavia, Pavia, Italy, and the TI/J.Kilby Analog Engineering Chair Professor at Texas A&M University, College Station. He is currently with the University of Pavia and an adjunct Professor at the University of Texas at Dallas. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the area of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more than 250 published papers, three books, and holds 15 patents.Dr. Maloberti was a 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institution of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS triode transistor transconductance for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects’ Evaluator and Reviewer and as a European Union expert in many Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs’ evaluator. He was Vice-President, Region 8, of the Editor of IEEE Circuits and Systems (CAS) Society from 1995 to 1997 and an Associate Editor of the IEEE Transcations on Circuits and Systems II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millennium Medal. He is the President of IEEE Sensors Council and a member of the Board of Governors of the IEEE CAS Society. He is also the member of the Italian Electrotechnical and Electronic Society (AEI) and the Editorial Board of Analog Integrated Circuits and Signal Processing.     

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.Paolo Rossi was born in Milan, Italy, in 1975. He received the Laurea degree (summa cum laude) in electrical engineering from the University of Pavia, Pavia, Italy, in 2000, where he is currently working toward the Ph.D. degree. His research interests are in the field of analog integrated circuits for wireless transceivers in CMOS and BiCMOS technology, with particular focus on the analysis and design of LNA and mixer for multi-standard applications.Francesco Svelto received the Laurea and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 1991 and 1995, respectively. From 1996 to 1997, he held a grant from STMicroelectronics to design CMOS RF circuits. In 1997, he was appointed Assistant Professor at the University of Bergamo, Italy, and in 2000, he joined the University of Pavia, where he is an Associate Professor. His current research interests are in the field of RF design and high-frequency integrated circuits for telecommunications. Dr. Svelto has been a member of the technical program committee of the IEEE Custom Integrated Circuits Conference since 2000 and the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) since 2003, and the European Solid State Circuits Conference in 2002. He served as Guest Editor of the March 2003 special issue of the IEEE Journal of Solid-State Circuits, of which he is currently an Associate Editor.Andrea Mazzanti was born in Modena (Italy) in 1976. He received the Laurea degree (summa cum Laude) in Electrical Engineering from the University of Modena and Reggio Emilia, Modena, Italy in 2001. Since 2001 he is pursuing his PhD in Electrical Engineering at University of Modena and Reggio Emilia, Italy. His major research interest are modelling of microwave semiconductor devices and design of CMOS RF integrated circuits, with particular focus on low noise oscillators and analog frequency dividers. During the summer of 2003 he was with Agere Systems, Allentown, PA as an internship student, working on the design of an highly integrated CMOS FM transmitter.Pietro Andreani received the M.S.E.E. from the University of Pisa, Italy, in 1988. He joined the Dept. of Applied Electronics, Lund University, Sweden, in 1990, where he contributed to the development of software tools for digital ASIC design. After working at the Dept. of Applied Electronics, University of Pisa, as a CMOS IC designer during 1994, he rejoined the Dept. of Applied Electronics in Lund as an Associate Professor, where he was responsible for the analog IC course package between 1995 and 2001, and where he received the Ph.D. degree in 1999. He is currently a Professor at the Center for Physical Electronics, ØrstedDTU, Technical University of Denmark, Kgs. Lyngby, Denmark, with analog/RF CMOS IC design as main research field.     

Active-Gm-RC Continuous-Time Biquadratic Cells

An analog CMOS low-pass Active-Gm-RC biquadratic cell is presented. The cell combines the advantage of GM-C filters (no parasitic poles) with the advantages of Active-RC filter (large linear range). Two additional digital-based circuits allow to control the pole frequency and to reduce the effects of the non-dominant poles. A 4th order low-pass Butterworth filter with a 2.11 MHz cut-off frequency and a DC-gain of 32 dB for UMTS receiver has been designed in a 0.18 μm CMOS technology with 1.8 V supply voltage. The filter exhibits a −93 dBV input-referred noise with a power consumption of 2.16 mW while the linearity performances corresponds to an in-band IIP3 of 4 dBm and an out-of-band IIP3 of 35 dBm. An Active Gm-RC band-pass cell is presented as possible alternative application. Stefano D'Amico was born in Tricase (Lecce), Italy, in 1976. He received the M.S. Degree in Electrical Engineering from the Politecnico di Bari, Italy. He is, currently, a Ph.D. student in the Department of Innovation Engineering at the University of Lecce, Italy. His research interests are in the area of low-power analog circuits with emphasis in baseband transceivers blocks design. Andrea Baschirotto was born in 1965 in Legnago (Verona), Italy. In 1989, he graduated in Electronic Engineering (summa cum laude) from the University of Pavia, Italy. In 1994, he received the Ph.D. degree in electrical engineering from the University of Pavia. In 1994, he joined the Department of Electronics, University of Pavia, as a Researcher (Assistant Professor). In 1998, he joined the Department of Innovation Engineering, University of Lecce, Italy, as an Associate Professor, where he is leading the Microelectronics Group. Since 1989, he has collaborated with STMicroelectronics, Cornaredo, Italy, on the design of ASICs. Since 1991, he has been associated with I.N.F.N. on the design and realization of read-out channels for high-energy physics experiments and space experiments. He collaborated with SMI's for the design of mixed signals ASICS. His main research interests are in the design of mixed analog/digital integrated circuits, in particular for low-power and/or high-speed signal processing. He has authored or co-authored more than 62 papers in international journals, more than 75 presentations at international conferences, 4 book chapters, and holds 25 industrial patents. In addition, he has co-authored more than 120 papers within research collaborations on high-energy physics experiments. Dr. Baschirotto was a guest editor for the IEEE Trans. Circuits Syst. II for the special issue on IEEE ISCAS 1998. He served IEEE Trans. Circuits Syst. II as an associate editor in the period 2000–2003. He is now serving IEEE Trans. Circuits Syst. I as an associate editor. He is a member of the International technical program Committee (ITPC) of ISSCC and of the TPC of ESSCIRC. He has been the TPC Chairman for ESSCIRC 2002 (the first time in which the conference was held jointly with ESSDERC and the largest attendance was achieved). He is the General Coordinator of a National PRIN Project on reconfigurable high-dynamic range gas sensor systems.     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock feedthrough noise. A model of clock feedthrough noise as compared with SPICE simulations exhibits less than 3% error. This research was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-687, the DARPA/ITO under AFRL Contract F29601-00-K-0182, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology—Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. Weize Xu received the B.S. degree from Nanjing University of Posts and Telecommunications, China in 1982, and the M.S. degrees from the University of Rhode Island in 1993, both in electrical engineering. Since 1997, he has been a senor research engineer and analog IC design specialist at Eastman Kodak Company. His research interests include high speed analog IC designs, pipelined A/D converter, low power switched capacitor circuit analysis and design, CMOS image sensor design, and analysis of noise in mixed signal ICs. He currently is a Ph.D candidate at the University of Rochester. Eby G. Friedman (S'78-M'79-SM'90-F'00) received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He also enjoyed a sabbatical at the Technion—Israel Institute of Technology during the 2000/2001 academic year. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 250 papers and book chapters, several patents, and the author or editor of seven books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock distribution networks. Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems, and Computers, a Member of the editorial boards of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing microelectronics Journal, and Journal of VLSI Signal Processing, a Member of the Circuits and Systems (CAS) Society Board of Governors, and a Member of the technical program committee of a number of conferences. He previously was the past Editor-in-Chief of the IEEE Transactions on VLSI Systems, a Member of the editorial board of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Chair of the IEEE Transactions on VLSI Systems steering committee, CAS liaison to the Solid-State Circuits Society, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the Electron Devices Chapter of the IEEE Rochester Section, Program or Technical chair of several IEEE conferences, Guest Editor of several special issues in a variety of journals, and a recipient of the Howard Hughes Masters and Doctoral Fellowships, an IBM University Research Award, an Outstanding IEEE Chapter Chairman Award, and a University of Rochester College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.     

Fast Converging Adaptive MMSE Multiuser Detector for DS-CDMA System

A fast converging adaptive minimum-mean-squared-error (MMSE) multiuser detector is proposed for direct-sequence code-division multiple-access (DS-CDMA) systems with severe near-far problem where the convergence rate of adaptive MMSE detectors for distinct users can be very different. It is shown that by successively cancelling the interference signals of strong power users, the convergence rate of the proposed detectors for weak power users can be significantly increased, which helps to reduce the length of training sequence for tracking. It is also shown that the order of cancellation and several important parameters required for interference cancellation can be determined from the convergence behavior of the proposed detector. Numerical results are presented to show that the proposed detector offers improved performance in various DS-CDMA environments.Zhiwei Mao received the B.Sc. degrees from Beijing University of Posts and Telecommunications (BUPT), Beijing, China in 1996 and 1999, respectively. Since 2000, she had been a Research Assistant and graduate student in the Department of Electrical and Coumputer Engineering, University of Victoria, Victoria, BC, Canada. She received the Ph.D. degree in electrical engineering in 2003. Currently, she is an Assistant Professor at Lakehead University, Thunder Bay, Ontario, Canada.Her research interests include wireless communications, multiuser detection, digital communications and digital singal processing.Vijay K. Bhargava received the B.Sc., M.Sc., and Ph.D. degree from Queens University, Kingston, ON, Canada in 1970, 1972 and 1974 respectively.Currently, he is a Professor and Head of the Department of Electrical and Computer Engineering at the University of British Columbia, Vancouver, Canada. Previously he was with the Univeristy of Victoria (1984–2003) and with Concordia University in Montréal (1976–1984). He is a co-author of the book Digital Communications by Satellite (New York: Wiley, 1981), co-editor of Reed-Solomon Codes and Their Applications (New York: IEEE, 1994) and co-editor of Communications, Information and Network Security (Boston: Kluwer, 2002). His research interest are in wireless communications.Dr. Bhargava is a Fellow of the B.C. Advanced Systems Institute, Engineering Institute of Canada (EIC), the IEEE, the Canadian Academy of Engineering and the Royal Society of Canada. He is a recipient of the IEEE Centennial Medal (1984), IEEE Canadas McNaughton Gold Medal (1995), the IEEE Haraden Pratt Award (1999), the IEEE Third Millennium Medal (2000), IEEE Graduate Teaching Award (2002), and the Eadie Medal of the Royal Society of Canada (2004).Dr. Bhargava is very active in the IEEE and was nominated by the IEEE Board of Director for the Office of IEEE President-Elect. Currently he serves on the Board of Communications Society. He is an Editor for the IEEE Transactions on Wireless Communications. He is a Past President of the IEEE Information Theory Society.     

Indoor location tracking using RSSI readings from a single Wi-Fi access point

This paper describes research towards a system for locating wireless nodes in a home environment requiring merely a single access point. The only sensor reading used for the location estimation is the received signal strength indication (RSSI) as given by an RF interface, e.g., Wi-Fi. Wireless signal strength maps for the positioning filter are obtained by a two-step parametric and measurement driven ray-tracing approach to account for absorption and reflection characteristics of various obstacles. Location estimates are then computed using Bayesian filtering on sample sets derived by Monte Carlo sampling. We outline the research leading to the system and provide location performance metrics using trace-driven simulations and real-life experiments. Our results and real-life walk-troughs indicate that RSSI readings from a single access point in an indoor environment are sufficient to derive good location estimates of users with sub-room precision. Gergely V. Záruba is an Assistant Professor of Computer Science and Engineering at The University of Texas at Arlington (CSE@UTA). He has received the Ph.D. degree in Computer Science from The University of Texas at Dallas in 2001, and the M.S. degree in Computer Engineering from the Technical University of Budapest, Department of Telecommunications and Telematics, in 1997. Dr. Záruba’s research interests include wireless networks, algorithms, and protocols, performance evaluation, current wireless and assistive technologies. He has served on many organizing and technical program committees for leading conferences and has guest edited journals. He is a member of the IEEE and its Communications Society. Manfred Huber is an Assistant Professor of Computer Science and Engineering at The University of Texas at Arlington (CSE@UTA). He received his M.S. and Ph.D. degrees in Computer Science from the University of Massachusetts, Amherst in 1993 and 2000, respectively. He obtained his “Vordiplom” from the University of Karlsruhe, Germany in 1990. Dr. Huber is the co-director of the Robotics and of the Learning and Planning Laboratory at CSE@UTA. His research interests are in reinforcement learning, autonomous robots, cognitive systems, and adaptive human-computer interfaces. He is a member of the IEEE, the ACM, and the AAAI. Farhad A. Kamangar is a Professor of Computer Science and Engineering at The University of Texas at Arlington (CSE@UTA). He has received the Ph.D. and M.S. degrees in Electrical Engineering from The University of Texas at Arlington in 1980 and 1977 respectively. He received his B.S. degree from the University of Teheran, Iran in 1975. Dr. Kamangar’s research interests include image processing, robotics, signal processing, machine intelligence and computer graphics. He is a member of the IEEE and the ACM. Imrich Chlamtac is the President of CREATE-NET and the Bruno Kessler Professor at the University of Trento, Italy and has held various honorary and chaired professorships in USA and Europe including the Distinguished Chair in Telecommunications Professorship at the University of Texas at Dallas, Sackler Professorship at Tel Aviv University and University Professorship at the Technical University of Budapest. In the past he was with Technion and UMass, Amherst, DEC Research. Dr. Imrich Chlamtac has made significant contribution to various networking technologies as scientist, educator and entrepreneur. Dr. Chlamtac is the recipient of multiple awards and recognitions including Fellow of the IEEE, Fellow of the ACM, Fulbright Scholar, the ACM Award for Outstanding Contributions to Research on Mobility and the IEEE Award for Outstanding Technical Contributions to Wireless Personal Communications. Dr. Chlamtac published close to four hundred refereed journal, book, and conference articles and is listed among ISI’s Highly Cited Researchers in Computer Science. Dr. Chlamtac is the co-author of four books, including the first book on Local Area Networks (1980) and the Amazon.com best seller and IEEE Editor’s Choice Wireless and Mobile Network Architectures, published by John Wiley and Sons (2000). Dr. Chlamtac has widely contributed to the scientific community as founder and Chair of ACM Sigmobile, founder and steering committee chair of some of the lead conferences in networking, including ACM Mobicom, IEEE/SPIE/ACM OptiComm, CreateNet Mobiquitous, CreateNet WiOpt, IEEE/CreateNet Broadnet, IEEE/CreateNet Tridentcom and IEEE/CreateNet Securecomm conferences. Dr. Chlamtac also serves as the founding Editor in Chief of the ACM/URSI/Springer Wireless Networks (WINET), the ACM/Springer Journal on Special Topics in Mobile Networks and Applications (MONET).     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

New 1.5-V CMOS second generation current conveyor based on wide range transconductor

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed CCII+ uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel and p-channel), to realize the input stage. This solution allows almost a rail-to-rail input and output operation; also it reduces the number of current mirrors needed in the input stage. The CCII+ is operating at supply voltages of ±0.75 V with a total standby current of 133 μA. The application of the proposed CCII+ to realize a MOS-C second order maximally flat low-pass filter is given. PSpice simulation results for the proposed CCII+ and its application are given. Ahmed H. Madian was born in Jeddah, Saudi Arabia in 1975. He received the B.Sc. degree with honors, and the M.Sc. degree in electronics and communications from Cairo University, Cairo, Egypt, in 1997, and 2001 respectively. He is currently a Research Assistant in the Electronics Engineering Department, Micro-Electronics Design Center, Egyptian Atomic Energy Authority, Cairo, Egypt. His research interests are in circuit theory; low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed/digital applications on filed programmable gate arrays. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the BSc degree with honors in 1994, the MSc degree in 1996, and the PhD degree in 1999, all from the Electronics and Communications Department, Cairo University, Egypt. He is currently an Associate Professor at the Electrical Engineering Department, Fayoum University, Egypt. He is currently also a visiting Associate Professor at the Electrical and Electronics Engineering Department, German University in Cairo, Egypt. In 2005, He was decorated with the Science Prize in Advanced Engineering Technology from the Academy of Scientific Research and technology. His research and teaching interests are in circuit theory, fully-integrated analog filters, high-frequency transconductance amplifiers, low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964,the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997-September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985-1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987-1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr Soliman gave a lecture at Nanyang Technological University, Singapore.Dr Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004-Now.     

A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

A new CMOS multimode digital pixel sensor dedicated to an implantable visual cortical stimulator

We describe in this paper a new CMOS multimode image pixel sensor (MIPS) dedicated to an implantable visual cortical stimulator. Each 16 μm × 16 μm pixel area contains a photodiode, with a fill factor of 22%, a comparator used to convert the pixel level from analog to digital (A/D) values and an 8-bit DRAM, resulting in a total of 44 transistors per pixel. The A/D conversions use one common digital to analog converter to deliver the voltage reference needed to determine the pixel voltage. Three selectable operation modes are combined in the proposed MIPS: A high dynamic range logarithmic mode, a linear integration mode, and a novel differential mode between two consecutive images. This last mode that allows 3D information is required for a visual cortical stimulator. A test chip has been fabricated in CMOS 0.18 μm technology and tested to validate the full operation of the different proposed modes. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec – ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International Conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 350 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE. Annie Trépanier received her Bachelor of Engineering Degree in Electrical Engineering in 2002 and her Master of Applied Sciences Degree in Microelectronics in 2005 from the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. She held a summer job at Nortel Networks and trained at Mindready. She is currently employed at Matrox, Montreal. Jean-Luc Trépanier received his Bachelor of Engineering Degree in Electrical Engineering in 2000 and his Master of Applied Sciences Degree in Microelectronics in 2003 from the Ecole Polytechnique de Montreal where he was a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. He started his first company, Olyxia inc., where he developed the soon to be released Cute Spider VoIP Network. He is also the founder and CEO of Nexyrius inc. which develops a new generation of embedded systems. Yves Audet received his M.Sc. degree from a joint program between the University of Sherbrooke, QC, Canada and Université Joseph Fourier in Grenoble, France. He completed his Ph.D. at Simon Fraser University, BC, Canada. He has been working for three years in Research and Development with Mitel Corporation before being hired as assistant professor at école Polytechnique of Montreal, QC, Canada, in 2001. His research interests are CMOS sensor arrays and mixed signal circuits. Roula Ghannoum received her Bachelor of Engineering Degree in Computer and Communications Engineering from the Lebanese American University, Byblos—Lebanon, in July 2005. She is currently pursuing her Master of Applied Sciences in Microelectronics at the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory working on image sensors as part of a global project that aims at restoring sight to the visually incapacitated.     

DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation

To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations. Seok-Bae Park received the B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Ohio State University, Columbus, Ohio. He is currently with Firstpass Technologies, Inc., Dublin, Ohio as a Senior RF and Mixed-Signal Design Engineer. His current interests include low voltage/low power CMOS RF/analog/mixed-signal integrated circuits and systems for wireless communications. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is Professor and The Founding Director of the Analog VLSI Lab, The Ohio State University. He advised the work of 40 PhD students and of 85 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has coedited and coauthored several books including a text on Analog VLSI Signal and Information Processing, McGraw Hill. His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

UbiqMuseum: A Bluetooth and Java Based Context-Aware System for Ubiquitous Computing

This paper evaluates the use of Bluetooth and Java based technologies in ubiquitous computing environments. Ubiquitous computing strongly depends on leveraging appropriate contextual information to users, according to their preferences and the environment in which they reside. We present UbiqMuseum – an experimental context-aware application that provides context-aware information to museum visitors. UbiqMuseum combines the productivity of Java with the universal connectivity provided by Bluetooth wireless technology. We describe the overall architecture and discuss the implementation steps taken to create our Bluetooth and Java based context-aware application. We demonstrate practicality of building a context-aware system by using UbiqMuseum as a proof of concept that integrates a combination of Bluetooth, WLAN and Ethernet LAN technologies. Finally we run some experiments in a small testbed to evaluate the performance and system behaviour. We evaluate the impact on throughput with varying packet size, coding types and device separation distance sending both images and text. We also present our findings in term of inquiry delay with respect to distance. Numerical results show that Bluetooth offers a relatively steady throughput up to 10 m while the inquiry delay does not increase significantly with distance. Juan-Carlos Cano is an assistant professor in the Department of Computer Engineering at the Polytechnic University of Valencia (UPV) in Spain. He earned an M.Sc. and a Ph.D. in computer science from the UPV in 1994 and 2002 respectively. Between 1995–1997 he worked as a programming analyst at IBM's manufacturing division in Valencia. His current research interests include power aware routing protocols for mobile ad hoc networks and pervasive computing. You can contact him at jucano@disca.upv.es. Pietro Manzoni received the MS degree in computer science from the “Universitá degli Studi" of Milan, Italy, in 1989, and the Ph.D. degree in computer science from the Polytechnic University of Milan, Italy, in 1995. He is an associate professor of computer science at the Polytechnic University of Valencia, Spain. His research activity is related to wireless networks protocol design, modeling, and implementation. He is member of the IEEE. C.-K. Toh is currently a Professor and Chair in Communication Networks at Queen Mary University of London, UK. He is also the Director of the UK Ad Hoc Wireless Consortium and Director of the Queen Mary/Fudan Joint Research Lab in Mobile Networking and Ubiquitous Computing. Concurrently, he is also an Honorary Professor with the University of Hong Kong and an Adjunct Professor at Fudan University, Shanghai. Previously, he was the Director of Research with TRW Tactical Systems in California, USA (now Northrop Grumman Corporation) and was responsible for DARPA and Army programs in communications and networking. He had also worked for Hughes Research, ALR, HP, and was a professor at GeorgiaTech and University of California, Irvine. CK is the recipient of the 2005 IEEE Kiyo Tomiyasu Technical Medal Award, for “pioneering contributions to communication protocols in ad hoc mobile wireless networks." He is the author of “Wireless ATM & Ad Hoc Networks" (Kluwer Press, 1996) and “Ad Hoc Mobile Wireless Networks" (Prentice Hall Engineering Title Best Seller, 2001–2003). He is a recipient of the ACM Recognition of Service Award, for co-founding ACM MobiHoc Conference. He is a co-recipient of the Korean Science & Engineering Foundation Best Journal paper Award for his work on ad hoc TCP. CK was formerly the Chairman of IEEE Communications Society Technical Committee on Computer Communications and Chairman of IEEE Subcommittee on Ad Hoc Mobile Wireless Networks. He was an IEEE Expert/Distinguished Lecturer and had served as a Steering Committee Member for IEEE WCNC Conference and IEEE Transaction on Mobile Computing. He was a member of IEEE Communications Society Meetings & Conferences Board. CK was an editor for IEEE Networks, IEEE JSAC, IEEE transactions on Wireless Communications, Journal on Communication Networks, and IEEE Distributed Systems. He is a Fellow of four societies: British Computer Society, the IEE, the Hong Kong Institution of Engineers and the New Zealand Computer Society. He received his Ph.D. degree in Computer Science from Cambridge University, England, and his executive education from Harvard.     

Self-Checking Voter for High Speed TMR Systems

In this paper we address the problem of faults possibly affecting voters of TMR systems and making them provide incorrect majority data, thus making the adoption of the TMR technique useless. We consequently instantiate the need for self-checking voting schemes and propose a new CMOS self-checking voter that, compared to alternate self-checking solutions, features the advantage of being faster, while requiring comparable power consumption and a small increase in area overhead.José Manuel Cazeaux received his degree in Electronic Engineering from the University of Mar del Plata (Argentina) in 2002. In 2003 he was awarded a MADESS grant and joined the Electronics Department of the University of Bologna, where he is currently working towards his PhD in Electronic Engineering and Computer Science. His research interests are fault modeling, on-line testing and fault-tolerance techniques. He is a IEEE Student Member of the Computer Society.Daniele Rossi obtained the degree in Electronic Engineering from the University of Bologna in 2001. He is currently working towards his PhD in Electronic Engineering and Computer Science at the same University. His research interests include on-line testing and fault-tolerance techniques, with particular focus on coding techniques for fault tolerant and low power buses and for crosstalk effects minimization. He is a Member of the IEEE Computer Society.Cecilia Metra obtained the degree in Electronic Engineering and the PhD degree in Electronic Engineering and Computer Science from the University of Bologna (Italy). Currently, she is an Associate Professor in Electronics at the University of Bologna (Italy). From 1998 to 2001, she has also been Visiting Scholar at the University of Washington, Seattle (USA), while in 2002 she has been Visiting Faculty Consultant for Intel, Santa Clara (CA). She is General Co-Chair of “The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems” 2005 and Program Co-Chair of the “IEEE Int. On-Line Testing Symposium” 2005. She has been Program Co-Chair of the “IEEE Int. On-Line Testing Symposium”, 2004, 2003, Program Co-Chair/General Co-Chair of the “IEEE Int. On-Line Testing Workshop”, 2002, 2001 and “The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems”, 1998, 1999. She is/has been Member of the Technical Program Committee of several International Conferences. She is an Associate Editor for the IEEE Transactions on Computers and a Member of the Editorial Board of the Journal of Electronic Testing: Theory and Applications (Springer) and of the Microelectronics Journal (Elsevier Science). Her research interests are in the field of fault-tolerance, with particular emphasis on modular redundant systems, on-line testing techniques, error recovery and correction, fault analysis and modeling, concurrent diagnosis. She is a Member of the IEEE Computer Society.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. Koichi Sato is a Ph.D. student in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He earned his B.S. in University of Tokyo, Japan in 1993. He worked for Automotive Development Center in Mitsubishi Electric Corporation where he was involved in lane and automobile recognition in vehicle video processing products such as automatic cruise control and drowsiness detection systems. He enrolled in the current University at 1998 and received an M.S in 2000. In his Master's thesis he worked on human tracking and human interaction recognition. His current work includes velocity extraction using the TSV transform, object tracking, and 3D object reconstruction. Brian L. Evans is a tenured Associate Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin. His research and teaching efforts are in embedded real-time signal and image processing systems. In signal processing, his research group is focused on the design and real-time software implementation of ADSL and VDSL transceivers, for high-speed Internet access. In image processing, his group is focused on the design and real-time software implementation of high-quality halftoning for desktop printers, smart image acquisition for digital still cameras, and 3-D sonar imaging systems. In signal and image processing, Dr. Evans has published over 100 refereed conference and journal papers. Dr. Evans is the primary architect of the Signals and Systems Pack for Mathematica, which has been on the market since October 1995. He was a key contributor to UC Berkeley's Ptolemy Classic electronic design automation environment for embedded systems, which has been successfully commercialized by Agilent and Cadence. His BSEECS (1987) degree is from the Rose-Hulman Institute of Technology, and his MSEE (1988) and PhDEE (1993) degrees are from the Georgia Institute of Technology. From 1993 to 1996, he was a post-doctoral researcher in the Ptolemy project at UC Berkeley. He is a member of the Design and Implementation of Signal Processing Systems Technical Committee of the IEEE Signal Processing Society, and a Senior Member of the IEEE. He is the recipient of a 1997 National Science Foundation CAREER Award. J.K. Aggarwal has served on the faculty of The University of Texas at Austin College of Engineering since 1964 and is currently Cullen Professor of Electrical and Computer Engineering and Director of the Computer and Vision Research Center. His research interests include computer vision and pattern recognition focusing on human motion. A Fellow of IEEE since 1976 and IAPR since 1998, he received the Senior Research Award of the American Society of Engineering Education in 1992, the 1996 Technical Achievement Award of the IEEE Computer Society and the graduate teaching award at The University of Texas at Austin in 1992. He has served as Chairman of the IEEE Computer Society Technical Committee on Pattern Analysis and Machine Intelligence (1987--1989); Director of the NATO Advanced Research Workshop on Multisensor Fusion for Computer Vision, Grenoble, France (1989); Chairman of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (1993), and President of the International Association for Pattern Recognition (1992--1994). He is a Life Fellow of IEEE and Golden Core member of IEEE Computer Society. He has authored and edited a number of books, chapters, proceedings of conferences, and papers.     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

Energy-aware on-demand routing protocols for wireless ad hoc networks

Energy use is a crucial design concern in wireless ad hoc networks since wireless terminals are typically battery-operated. The design objectives of energy-aware routing are two folds: Selecting energy-efficient paths and minimizing the protocol overhead incurred for acquiring such paths. To achieve these goals simultaneously, we present the design of several on-demand energy-aware routing protocols. The key idea behind our design is to adaptively select the subset of nodes that are required to involve in a route-searching process in order to acquire a high residual-energy path and/or the degree to which nodes are required to participate in the process of searching for a low-power path in networks wherein nodes have transmission power adjusting capability. Analytical and simulation results are given to demonstrate the high performance of the designed protocols in energy-efficient utilization as well as in reducing the protocol overhead incurred in acquiring energy-efficient routes. Baoxian Zhang received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Northern Jiaotong University, Beijing, China in 1994, 1997, and 2000, respectively. From January 2001 to August 2002, he was working with Department of Electrical and Computer Engineering at Queen’s University in Kingston as a postdoctoral fellow. He is currently a research scientist with the School of Information Technology and Engineering (SITE) of University of Ottawa in Ottawa, Ontario, Canada. He has published over 40 refereed technical papers in international journals and conference proceedings. His research interests include routing algorithm and protocol design, QoS management, wireless ad hoc and sensor networks, survivable optical networks, multicast communications, and performance evaluation. He is a member of the IEEE. Hussein Mouftah joined the School of Information Technology and Engineering (SITE) of the University of Ottawa in September 2002 as a Canada Research Chair (Tier 1) Professor in Optical Networks. He has been with the Department of Electrical and Computer Engineering at Queen’s University (1979-2002), where he was prior to his departure a Full Professor and the Department Associate Head. He has three years of industrial experience mainly at Bell Northern Research of Ottawa, now Nortel Networks (1977-79). He has spent three sabbatical years also at Nortel Networks (1986-87, 1993-94, and 2000-01), always conducting research in the area of broadband packet switching networks, mobile wireless networks and quality of service over the optical Internet. He served as Editor-in-Chief of the IEEE Communications Magazine (1995-97) and IEEE Communications Society Director of Magazines (1998-99) and Chair of the Awards Committee (2002-2003). He is a Distinguished Speaker of the IEEE Communications Society since 2000. Dr. Mouftah is the author or coauthor of five books, 22 book chapters and more than 700 technical papers and 8 patents in this area. He is the recipient of the 1989 Engineering Medal for Research and Development of the Association of Professional Engineers of Ontario (PEO), and the Ontario Distinguished Researcher Award of the Ontario Innovation Trust. He is the joint holder of the Best Paper Award for a paper presented at SPECTS’2002, and the Outstanding Paper Award for papers presented at the IEEE HPSR’2002 and the IEEE ISMVL’1985. Also he is the joint holder of a Honorable Mention for the Frederick W. Ellersick Price Paper Award for Best Paper in the IEEE Communications Magazine in 1993. He is the recipient of the IEEE Canada (Region 7) Outstanding Service Award (1995). Also he is the recipient of the 2004 IEEE Communications Society Edwin Howard Armstrong Achievement Award, and the 2004 George S. Glinski Award for Excellence in Research of the Faculty of Engineering, University of Ottawa. Dr. Mouftah is a Fellow of the IEEE (1990) and Fellow of the Canadian Academy of Engineering (2003).