Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

On-Chip Pseudorandom MEMS Testing

This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for MEMS. The technique is based on Impulse Response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS). The MLS approach is capable of providing vastly superior dynamic range in comparison to the straightforward technique using an impulse excitation and is thus an optimal solution for measurements in noisy environments and for low-power test signals. The use of a pseudo-random sequence makes the practical on-chip implementation very efficient in terms of the extra hardware required for on-chip testing. We will demonstrate the use of this technique for an on-chip fast and accurate broadband determination of MEMS behaviour, in particular for the characterisation of cantilever MEMS structures, determining their mechanical and thermal behaviour using just electrical tests.Libor Rufer has received Engineering and PhD degrees from the Czech Technical University, Prague, Czech Republic. Until 1993 he was with the Faculty of Electrical Engineering of the Czech Technical University, Prague and since 1994, he is Associate Professor at the Joseph Fourier University, Grenoble, France. In 1998, he joined the Microsystems research team of the TIMA Laboratory. Currently he is a member of the Reliable Mixed-signal Systems Group of the same Laboratory. His expertise and research interests pertain MEMS-based sensors and actuators, electro-acoustic and electro-mechanical transducers, their modelling, applications, associated measurement techniques, and analogue and mixed-signal system test.Salvador Mir has an Industrial Engineering (Electrical, 1987) degree from the Polytechnic University of Catalonia, Barcelona, Spain, and M.Sc. (1989) and Ph.D. (1993) degrees in Computer Science from the University of Manchester, UK. He is a researcher of Centre National de la Recherche Scientifique, France, and he is leading the RMS (Reliable Mixed-signal Systems) Group at TIMA Laboratory in Grenoble, France. He is the author of many research papers and editor of two books on silicon microsystems. His research interests include analogue, mixed-signal, RF and microsystem design and test, and applications of Artificial Intelligence to Computer-Aided Design.Emmanuel Simeu received Electrical Engineering degree, DEA and Ph.D. in Automatic Control from National Polytechnic Institute of Grenoble in 1987, 1988 and 1992, respectively. He is Associate Professor of Automatic Control and Electrical engineering in Joseph Fourier University of Grenoble. He is also a researcher in the RMS Group at TIMA Laboratory. His research interests include system modelling, reliability of integrated systems, online testing of analogue, digital and mixed signal systems.Christian Domingues was born in Lyon, France, in 1978. He received a Master degree in Microelectronics from the Institut National Polytechnique de Grenoble, France, in 2001. He is currently pursuing a Ph.D. degree at TIMA Laboratory in Grenoble, France. His research interests include mixed-signal integrated circuit design, and micromachined sensors and actuators.     

Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies

Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used.Paolo Rossi was born in Milan, Italy, in 1975. He received the Laurea degree (summa cum laude) in electrical engineering from the University of Pavia, Pavia, Italy, in 2000, where he is currently working toward the Ph.D. degree. His research interests are in the field of analog integrated circuits for wireless transceivers in CMOS and BiCMOS technology, with particular focus on the analysis and design of LNA and mixer for multi-standard applications.Francesco Svelto received the Laurea and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 1991 and 1995, respectively. From 1996 to 1997, he held a grant from STMicroelectronics to design CMOS RF circuits. In 1997, he was appointed Assistant Professor at the University of Bergamo, Italy, and in 2000, he joined the University of Pavia, where he is an Associate Professor. His current research interests are in the field of RF design and high-frequency integrated circuits for telecommunications. Dr. Svelto has been a member of the technical program committee of the IEEE Custom Integrated Circuits Conference since 2000 and the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) since 2003, and the European Solid State Circuits Conference in 2002. He served as Guest Editor of the March 2003 special issue of the IEEE Journal of Solid-State Circuits, of which he is currently an Associate Editor.Andrea Mazzanti was born in Modena (Italy) in 1976. He received the Laurea degree (summa cum Laude) in Electrical Engineering from the University of Modena and Reggio Emilia, Modena, Italy in 2001. Since 2001 he is pursuing his PhD in Electrical Engineering at University of Modena and Reggio Emilia, Italy. His major research interest are modelling of microwave semiconductor devices and design of CMOS RF integrated circuits, with particular focus on low noise oscillators and analog frequency dividers. During the summer of 2003 he was with Agere Systems, Allentown, PA as an internship student, working on the design of an highly integrated CMOS FM transmitter.Pietro Andreani received the M.S.E.E. from the University of Pisa, Italy, in 1988. He joined the Dept. of Applied Electronics, Lund University, Sweden, in 1990, where he contributed to the development of software tools for digital ASIC design. After working at the Dept. of Applied Electronics, University of Pisa, as a CMOS IC designer during 1994, he rejoined the Dept. of Applied Electronics in Lund as an Associate Professor, where he was responsible for the analog IC course package between 1995 and 2001, and where he received the Ph.D. degree in 1999. He is currently a Professor at the Center for Physical Electronics, ØrstedDTU, Technical University of Denmark, Kgs. Lyngby, Denmark, with analog/RF CMOS IC design as main research field.     

A low-power, second-order Δ/Σ modulator using a single class-AB op-amp for voice-band applications

The design of a power-efficient second-order Δ/Σ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. Aminghasem Safarian received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 2000, 2002, respectively. Since 2003 he is a research assistant at University of California, Irvine, working toward his Ph.D. degree in electrical engineering emphasizing on RF IC design for wireless communication systems. During the summer of 2005, he was with Broadcom Corporation, Irvine, CA, where he developed integrated receivers for RFID and WCDMA applications. Farzad Sahandiesfanjani was born in Tabriz, Iran in 1976. He received the B.S. and M.S. degrees in electronics from Sharif University of Technology, Tehran, Iran, in 1998 and 2000, respectively. The subject of his thesis was the design of 4th order cascade delta-sigma modulator for ADSL Analog Front End. From 1998 to 2003, he was with Emad Semicon Co., Tehran, Iran, where he designed circuits for voice application such as CODEC and SLIC chip. He also designed a 3rd order single loop class-D delta-sigma modulator for audio application. He joined Tripath Technology Inc., San Jose, CA, in 2003 and has been working on the design of analog and mixed-signal circuits for class-T audio power amplifier. He is also author of one patent for inductor-less switching audio power amplifier and also co-author of 3 more pending patents and 4 papers. Payam Heydari (S'98–M'00) received the B.S. and M.S. degrees (with honors) in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, Murray Hill, NJ, where he worked on noise analysis in deep submicron very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who's Who in America. Dr. Heydari is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—part I. He currently serves on the Technical Program Committees of Custom Integrated Circuits Conference (CICC), International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003. Mojtaba Atarodi received his Ph.D degree from USC (the University of Southern California, Los Angeles), in electrical engineering Electro-physics in 1993, his M.S from University of California at Irvine, and his B.SEE from the Tehran Polytechnic University with first Grade honor. Following his Ph.D completion, he was with Linear Technology Corporation from 1993 to 1996 as an analog design engineer. He has been with Sharif University of Technology as an Assistant and Visiting Professor since 1997. The Author of more than 50 technical journal and conference papers an a book on Analog CMOS IC Design, Dr Atarodi’s main research interests are analog and RF IC system, circuit, and signal processing design as well as analog synthesis tools. Having held several management and consulting positions during the last 15 years in the US industry, he holds one US patent in analog highly linear tunable Operational Transconductance Amplifiers and has applied for 5 more US patents as well.     

An analysis of high-frequency noise in RF active CMOS mixers

An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and double-balanced architectures is presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and the channel’s thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power is studied. Experimental results verify the accuracy of the analytical model. Payam Heydari (S’98–M’00) received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, RF, and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who’s Who in America. Dr. Heydari Professor Heydari has been the Associate Editor of IEEE TRANS. ON CIRCUITS AND SYSTEMS, I, since 2006. He currently serves on the Technical Program Committees of International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003.     

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization for droplet-based microfluidic arrays. We first formulate the test planning problem and prove that it is NP-hard. We then describe an optimization method based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-hard nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, the heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost. This research was supported in part by the National Science Foundation under grant number IIS-0312352. A preliminary version of this paper appeared in Proc. European Test Symposium. pp. 72–77, 2004 Fei Su received the B.E. and the M.S. degrees in automation from Tsinghua University, Beijing, China, in 1999 and 2001, respectively, and the M.S. degree in electrical and computer engineering from Duke University, Durham, NC, in 2003. He is now a Ph.D. candidate in electrical and computer engineering at Duke University. His research interests include design and testing of mixed-technology microsystems, electronic design automation, mixed-signal VLSI design, MEMS modeling and simulation. Sule Ozev received her B.S. degree in Electrical Engineering at Bogazici University in 1995, and her M.S. and Ph.D. degrees in Computer Science and Engineering at University of California, San Diego in 1998 and 2002 respectively. Since 2002, she has been a faculty member at Duke University, Electrical and Computer Engineering Department. Her research interests include RF circuit analysis and testing, process variability analysis, and mixed-signal testing. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Associate Professor of Electrical and Computer Engineering at Duke University. Dr Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. His current research projects include: design and testing of system-on-chip integrated circuits; design automation of microfluidics-based biochips; microfluidics-based chip cooling; distributed sensor networks. Dr Chakrabarty has authored three books Microelectrofluidic Systems: Modeling and Simulation (CRC Press, 2002), Test Resource Partitioning for System-on-a-Chip (Kluwer, 2002), and Scalable Infrastructure for Distributed Sensor Networks (Springer, 2005) 3/4 and edited the book volume SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Kluwer 2002). He has published over 200 papers in journals and refereed conference proceedings, and he holds a US patent in built-in self-test. He is a recipient of best paper awards at the 2005 IEEE International Conference on Computer Design and 2001 IEEE Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany. Dr Chakrabarty is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems, and an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He a member of the editorial board for Sensor Letters and Journal of Embedded Computing and he serves as a subject area editor for the International Journal of Distributed Sensor Networks. He has also served as an Associate Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. He is a senior member of IEEE, a member of ACM and ACM SIGDA, and a member of Sigma Xi. He serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. He served as the Program Co-Chair for the 2005 IEEE Asian Test Symposium.     

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

In recent years, Defect Oriented Testing (DOT) has been investigated as an alternative testing method for analog circuits. In this paper, we propose a wavelet transform based dynamic supply current (IDD) analysis technique for detecting catastrophic and parametric faults in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier transform which decomposes a signal in frequency components only. Simulation results on benchmark circuits show that wavelet transform has higher fault detection sensitivity than Fourier or time-domain methods and hence, can be considered very promising for defect oriented testing of analog circuits. Effectiveness of wavelet transform based DOT amidst process variation and measurement noise is studied.This research is supported in part by MARCO GSRC under contract number SA3273JB.A paper based on this work was presented at the Fourth IEEE Latin American Test Workshop, Natal, Brazil, February 2003.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN.He has worked in the EDA industry on RTL synthesis and verification since 2000. His research interest includes defect-based testing, diagnosis, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN.He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings—Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Performance Analysis of Header Compression Schemes in Heterogeneous Wireless Multi–Hop Networks

Wireless multi–hop networks are becoming more popular and the demand for multimedia services in these networks rises with the number of their implementations. Header compression schemes that compress the IP/UDP/RTP headers to save bandwidth for multimedia streams were typically evaluated only for individual links, not taking into account the savings that can be achieved using header compression over a complete path. In this paper, we evaluate the performance of three categories of header compression schemes: (i) delta coding, (ii) framed delta coding, and (iii) framed referential coding. We evaluate the performance for these schemes on reliable and unreliable links. We then extend our evaluations to several links constituting a path. As nodes in multi–hop ad-hoc and mesh networks may differ with respect to their capabilities, we assume in our evaluation that (forwarding) nodes may not be able or choose not to perform header compression. We find that the framed referential header compression scheme is the most suitable scheme in case that no or long-delay feedback channels exist. We additionally compare the packet drop savings due to header compression and the combined savings of compression and drops. We again find that the framed referential coding scheme exhibits good performance that can lead to significant header compression and packet drop savings for reasonable bit error rates. Patrick Seeling is a Faculty Research Associate in the Department of Electrical Engineering at Arizona State University (ASU), Tempe. He received the Dipl.-Ing. degree in Industrial Engineering and Management (specializing in electrical engineering) from the Technical University of Berlin (TUB), Germany, in 2002. He received his Ph.D. in electrical engineering from Arizona State University, Arizona, in 2005. His research interests are in the area of multimedia communications in wired and wireless networks and engineering education. He is a member of the IEEE and the ACM. Martin Reisslein is an Associate Professor in the Department of Electrical Engineering at Arizona State University (ASU), Tempe. He received the Dipl.-Ing. (FH) degree from the Fachhochschule Dieburg, Germany, in 1994, and the M.S.E. degree from the University of Pennsylvania, Philadelphia, in 1996. Both in electrical engineering. He received his Ph.D. in systems engineering from the University of Pennsylvania in 1998. During the academic year 1994–1995 he visited the University of Pennsylvania as a Fulbright scholar. From July 1998 through October 2000 he was a scientist with the German National Research Center for Information Technology (GMD FOKUS), Berlin and lecturer at the Technical University Berlin. From October 2000 through August 2005 he was an Assistant Professor at ASU. He is editor-in-chief of the IEEE Communications Surveys and Tutorials and has served on the Technical Program Committees of IEEE Infocom, IEEE Globecom, and the IEEE International Symposium on Computer and Communications. He has organized sessions at the IEEE Computer Communications Workshop (CCW). He maintains an extensive library of video traces for network performance evaluation, including frame size traces of MPEG-4 and H.263 encoded video, at http://trace.eas.asu.edu. He is co-recipient of the Best Paper Award of the SPIE Photonics East 2000 – Terabit Optical Networking conference. His research interests are in the areas of Internet Quality of Service, video traffic characterization, wireless networking, optical networking, and engineering education. Tatiana K. Madsen has received her M.Sc. and Ph.D. degrees in Mathematics from Moscow State University, Russia in 1997 and 2000, respectively. In 2001 she joined Dept. of Communication Technology, Aalborg University, Denmark where she is currently an Assistant Professor. Her research interests lie within the areas of wireless networking with the focus on IP header compression techniques and mathematical modeling of wireless protocols behavior. Frank Fitzek is an Associate Professor in the Department of Communication Technology, Unversity of Aalborg, Denmark heading the Future Vision gorup. He received his diploma (Dipl.-Ing.) degree in electrical engineering from the University of Technology – Rheinish-Westflische Technische Hochschule (RWTH) – Aachen, Germany, in 1997 and his Ph.D. (Dr.-Ing.) in Electrical Engineering from the Technical Univeristy Berlin, Germany in 2002 for quality of service support in wireless CDMA networks. As a visiting student at the Arizona State University he conducted research in the field of video services over wireless networks. He co-founded the start-up company acticom GmbH in Berlin in 1999. In 2002 he was Adjunct Professor at the University of Ferrara, Italy giving lectures on wireless communications and conducting research on multi-hop networks. In 2005 he won the YRP award for the work on MIMO MDC. His current research interests are in the areas of 4G wireless communication networks and cooperative networking. Dr. Fitzek serves on the Editorial Board of the IEEE Communications Surveys and Tutorials.     

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Wavelet transform has the property of resolving signal in both time and frequency unlike Fourier transform. In this work, we show that time-domain information obtained from wavelet analysis of supply current can be used to test the frequency specification of analog filters efficiently. The pole/zero locations in the frequency response of analog filters shift due to change in component values with process variations. It is essential to test the filters for the shift in frequency response and fix it during production test. Wavelet analysis of supply current can be a promising alternative to test frequency specification of analog filters, since it needs only one AC stimulus and is virtually unaffected by transistor threshold variation. Simulation results on two test circuits demonstrate that we can estimate pole/zero shift with less than 3% error using only one measurement, which requires about 18 measurements in the conventional technique.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN, USA. He has worked in the EDA industry on RTL synthesis and verification for about three years. His research interest includes design methodologies for high-performance low-power testable VLSI system, defect-based testing, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN, USA. He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Extremely-Wide-Range Supply-Independent CMOS Voltage References for Telemetry-Powering Applications

This paper reports a voltage reference circuit in standard CMOS process. It exhibits excellent supply independency for a wide input voltage range, which is of great importance in telemetry-powered systems. This circuit is based on the well-known V_GS-reference supply-independent current reference circuit, but it is designed to serve as a voltage reference. While the reference current generated by this circuit varies with the supply voltage, a self-compensating mechanism can be found in voltage-mode operation of the circuit that results in a supply-independent reference voltage. This supply independency is well observed in the static operation of the circuit over an extremely wide input range, as well as in its dynamic behavior for high frequency ripples on the input voltage. Based on the proposed idea, a multi-output voltage reference and a CMOS DC level shifter are also designed. The proposed voltage reference circuits have been fabricated using MOSIS 1.6 μm standard CMOS process. The basic voltage reference provides 957 μV/V static supply dependency, rejects input ripples of up to 8 MHz by 60± 3dB, and consumes only 15.8–36.9 μA when the input voltage varies in the range 2.6–12 V. Amir M. Sodagar received the B.S. degree from K.N. Toosi (KNT) University of Technology, Tehran, Iran, and M.S. and Ph.D. degrees from Iran University of Science & Technology (IUST), Tehran, Iran all in Electrical Engineering in 1992, 1995, and 2000, respectively. From 1992 to 2000 he was with S. Rajaee University as a Lecturer. After receiving the Ph.D. degree until 2002 he was with the NSF Engineering Research Center for Wireless Integrated Micro Systems (WIMS), Electrical Engineering & Computer Science (EECS) Dept., University of Michigan as a Post-Doctoral Research Fellow. From 2002 to 2004 he was with S. Rajaee University and KNT University of Technology as an Assistant Professor and an Adjunct Professor, respectively, and since 2004 he has been with the University of Michigan as an Associate Visiting Research Scientist. Dr. Sodagar was known as the Outstanding Electrical Engineering Graduate Student of the IUST in 1995, and receiv ed the IUST's Best Ph.D. Research Achievement Award in 2000. He was also the recipient of S. Rajaee University's Distinguished Faculty Member Award for “1998–1999” and “1999–2000” academic years, and S. Rajaee University's Distinguished Researcher Award for “2002–2003” academic year. He was involved in the design of integrated circuits in collaboration with the Center for Semiconductor Research and Fabrication from 1994 to 1995, VLSI Circuits & Systems Laboratory at the University of Tehran from 1997 to 1998, and EMAD Semicon Company from 1998 to 2000. He has authored one book, authored/co-authored more than 20 journal and conference papers, and served as the technical paper reviewer for several IEEE journals/transactions and also conferences. Dr. Sodagar's research interests are generally in the field of mixed-signal integrated circuit design, and focused on: integrated circuits for neural recording & stimulation, telemetry powering and control of implantable microsystems, frequency synthesizers, analog building blocks, and transistor-level implementations of digital logic families. Khalil Najafi (IEEE S '84, M '86, SM '97, F'00) received the B.S., M.S., and the Ph.D. degree in 1980, 1981, and 1986 respectively, all in Electrical Engineering from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. From 1986–1988 he was employed as a Research Fellow, from 1988–1990 as an Assistant Research Scientist, from 1990–1993 as an Assistant Professor, from 1993–1998 as an Associate Professor, and since September 1998 as a Professor and the Director of the Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan. His research interests include: micromachining technologies, micromachined sensors, actuators, and MEMS; analog integrated circuits; implantable biomedical microsystems; micropackaging; and low-power wireless sensing/actuating systems. Dr. Najafi was awarded a National Science Foundation Young Investigator Award from 1992–1997, was the recipient of the Beatrice Winner Award for Editorial Excellence at the 1986 International Solid-State Circuits Conference, of the Paul Rappaport Award for co-authoring the Best Paper published in the IEEE Transactions on Electron Devices, and of the Best Paper Award at ISSCC 1999. In 2003 he received the EECS Outstanding Achievement Award, in 2001 he received the Faculty recognition Award, and in 1994 the University of Michigan's “Henry Russel Award” for outstanding achievement and scholarship, and was selected as the “Professor of the Year” in 1993. In 1998 he was named the Arhtur F. Thurnau Professor for outstanding contributions to teaching and research, and received the College of Engineering's Research Excellence Award. He has been active in the field of solid-state sensors and actuators for more than twenty years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid-State Sensors and Actuators Workshop, and the IEEE/ASME Micro Electromechanical Systems (MEMS) Conference. Dr. Najafi is the Editor for Solid-State Sensors for IEEE Transactions on Electron Devices, an Associate Editor for the Journal of Micromechanics and Microengineering, Institute of Physics Publishing, and an editor for the Journal of Sensors and Materials. He also served as the Associate Editor for IEEE Journal of Solid-State Circuits from 2000–2004, and the associate editor for IEEE Trans. Biomedical Engineering from 1999–2000. He is a Fellow of the IEEE.     

Cross-layer optimization for end-to-end rate allocation in multi-radio wireless mesh networks

In this paper, we study rate allocation for a set of end-to-end communication sessions in multi-radio wireless mesh networks. We propose cross-layer schemes to solve the joint rate allocation, routing, scheduling, power control and channel assignment problems with the goals of maximizing network throughput and achieving certain fairness. Fairness is addressed using both a simplified max-min fairness model and the well-known proportional fairness model. Our schemes can also offer performance upper bounds such as an upper bound on the maximum throughput. Numerical results show that our proportional fair rate allocation scheme achieves a good tradeoff between throughput and fairness. Jian Tang is an assistant professor in the Department of Computer Science at Montana State University. He received the Ph.D. degree in Computer Science from Arizona State University in 2006. His research interest is in the area of wireless networking and mobile computing. He has served on the technical program committees of multiple international conferences, including ICC, Globecom, IPCCC and QShine. He will also serve as a publicity co-chair of International Conference on Autonomic Computing and Communication Systems (Autonomics’2007). Guoliang Xue is a Full Professor in the Department of Computer Science and Engineering at Arizona State University. He received the Ph.D. degree in Computer Science from the University of Minnesota in 1991 and has held previous positions at the Army High Performance Computing Research Center and the University of Vermont. His research interests include efficient algorithms for optimization problems in networking, with applications to fault tolerance, robustness, and privacy issues in networks ranging from WDM optical networks to wireless ad hoc and sensor networks. He has published over 150 papers in these areas. His research has been continuously supported by federal agencies including NSF and ARO. He is the recipient of an NSF Research Initiation Award in 1994 and an NSF-ITR Award in 2003. He is an Associate Editor of Computer Networks (COMNET), the IEEE Network Magazine, and Journal of Global Optimization. He has served on the executive/program committees of many IEEE conferences, including INFOCOM, SECON, IWQOS, ICC, GLOBECOM and QShine. He is the General Chair of IEEE IPCCC’2005, a TPC co-Chair of IPCCC’2003, HPSR’2004, IEEE Globecom’2006 Symposium on Wireless Ad Hoc and Sensor Networks, IEEE ICC’2007 Symposium on Wireless Ad Hoc and Sensor Networks, and QShine’2007. He is a senior member of IEEE. Weiyi Zhang received the M.E. degree in 1999 from Southeast University, China. Currently he is a Ph.D. student in the Department of Computer Science and Engineering at Arizona State University. His research interests include reliable communication in networking, protection and restoration in WDM networks, and QoS provisioning in communication networks.     

A Prototype Bandpass Sigma-Delta Modulator Employing Crystal Resonator

This paper describes an initial work on a second-order bandpass Sigma-delta modulator employing crystal resonator. The aim of this work is to explore the possibilities of realizing bandpass sigma-delta modulator using non-electronic resonators, such as micro-mechanical resonators. The initial study is based on crystal resonators as they have similar characteristics as the other types of resonator and are readily available. In order to obtain the desired loop transfer function, a compensation circuit is proposed to cancel the anti-resonance in the crystal resonator. The modulator chip is fabricated in a 0.6-μ m CMOS process. The bandpass noise shaping is demonstrated in the experiment with a 1- and 8-MHz crystal resonator, respectively. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R.China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. He is a Senior Member of IEEE. Xiaofeng Wang was born in Shangqiu, China, in 1980. He received B.Eng. degree from Northwestern Polytechnical University, Xi'an, China, in 2000 and M. Eng. degree from National University of Singapore, Singapore, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree at Tufts University, Medford, USA. His research is on high speed ADC design. Wai Hoong Sun was born in Taiping, Malaysia in 1976. He received the B. App. Sc. (Honours) degree in electrical engineering from the University of Toronto, Canada in 1999. After graduating, he joined Sharp Electronics Singapore as an R&D Engineer where he was involved in FPGA and digital IC design of display related circuits. In 2001 and 2002, he did full time research in the National University of Singapore on bandpass sigma-delta modulators. During that period, he was also a Graduate Tutor in electronics for second year electrical and computer engineering students. He then joined Philips Electronics Singapore in 2002 as a Lead Engineer. He did board-level designs for LCD and plasma televisions. He was also development project leader for a project that was successful in bringing to the market a range of LCD and plasma televisions. Currently, he is a Hardware Architect where he is responsible for the system-level electrical design of the television board.     

Channel Sharing Scheme for Packet-Switched Cellular Networks

In this paper, we study an approach for sharing channels to improve network utilization in packet-switched cellular networks. Our scheme exploits unused resources in neighboring cells without the need for global coordination. We formulate a minimax approach to optimizing the allocation of channels in this sharing scheme. We develop a measurement-based distributed algorithm to achieve this objective and study its convergence. We illustrate, via simulation results, that the distributed channel sharing scheme performs significantly better than the fixed channel scheme over a wide variety of traffic conditions. This research was supported in part by the National Science Foundation through grants ECS-0098089, ANI-0099137, ANI-0207892, ANI-9805441, ANI-0099137, and ANI-0207728, and by an Indiana 21st century grant. A conference version of this paper appeared in INFOCOM 99. This work was done when all the authors were at Purdue University. Suresh Kalyanasundaram received his Bachelors degree in Electrical and Electronics Engineering and Masters degree in Physics from Birla Institute of Technology and Science, Pilani, India in 1996. He received his Ph.D. from the School of Electrical and Computer Engineering, Purdue University, in May 2000. Since then he has been with Motorola, working in the area of performance analysis of wireless networks. Junyi Li received his B.S. and M.S. degrees from Shanghai Jiao Tong University, and Ph.D. degree from Purdue University. He was with the Department of Digital Communications Research at Bell Labs, Lucent Technologies from 1998 to 2000. In 2000 as a founding member he jointed Flarion Technologies, where he is now Director of Technology. He is a senior member of IEEE. Edwin K.P. Chong received the B.E.(Hons.) degree with First Class Honors from the University of Adelaide, South Australia, in 1987; and the M.A. and Ph.D. degrees in 1989 and 1991, respectively, both from Princeton University, where he held an IBM Fellowship. He joined the School of Electrical and Computer Engineering at Purdue University in 1991, where he was named a University Faculty Scholar in 1999, and was promoted to Professor in 2001. Since August 2001, he has been a Professor of Electrical and Computer Engineering and a Professor of Mathematics at Colorado State University. His current interests are in communication networks and optimization methods. He coauthored the recent book, An Introduction to Optimization, 2nd Edition, Wiley-Interscience, 2001. He was on the editorial board of the IEEE Transactions on Automatic Control, and is currently an editor for Computer Networks. He is an IEEE Control Systems Society Distinguished Lecturer. He received the NSF CAREER Award in 1995 and the ASEE Frederick Emmons Terman Award in 1998. Ness B. Shroff received his Ph.D. degree from Columbia University, NY in 1994. He is currently an Associate Professor in the School of Electrical and Computer Engineering at Purdue University. His research interests span the areas of wireless and wireline communication networks. He is especially interested in fundamental problems in the design, performance, scheduling, capacity, pricing, and control of these networks. His research is funded by various companies such as Intel, Hewlett Packard, Nortel, AT&T, and L. G. Electronics; and government agencies such as the National Science Foundation, Indiana Dept. of Transportation, and the Indiana 21st Century fund. Dr. Shroff is an editor for IEEE/ACM Trans. on Networking and the Computer Networks Journal, and past editor of IEEE Communications Letters. He was the conference chair for the 14th Annual IEEE Computer Communications Workshop (in Estes Park, CO, October 1999) and program co-chair for the symposium on high-speed networks, Globecom 2001 (San Francisco, CA, November 2000). He is also the Technical Program co-chair for IEEE INFOCOM'03 and panel co-chair for ACM Mobicom'02. He received the NSF CAREER award in 1996.     

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

A new dual-band, 2.4 and 5.2 GHz, combined LNA, which can operate at 1 V supply only, for WLAN application is presented. The switched transistor technique is used in the LNA. It could match the input port in two frequency bands and reduce one on-chip spiral inductor usage compared with [1, 2]. Theoretical analysis and transistor level simulation results using 0.18 μm CMOS process from Chartered Semiconductor are presented to demonstrate this idea. Wang-Chi Cheng received his B.Eng., M.Phil., and Ph.D. degrees in Electronic Engineering of the Chinese University of Hong Kong (CUHK) in 1999, 2001 and 2004. His research achievements during M.Phil. and Ph.D. studies were in the field of low voltage receiver front-end circuits design with CMOS technology. He joined the Electrical and Electronic Engineering department of Nanyang Technological University (NTU), Singapore, in May 2005 as a Research Fellow. Now, he is a Senior Engineer in charge of the UWB transceiver IC design in Hong Kong Applied Science and Technology Research Institute (ASTRI). His current research interests include 802.11 A/B WLAN and UWB transceiver design. He is also a paper reviewer of the IEEE Microwave and Wireless Components Letters. Jian-Guo Ma received his B.Sc. and M.Sc. in 1982 and 1988 respectively with honors from Lanzhou university of Chain, and Doctoral Degree in Engineering from Gerhard-Mercator University of Germany in 1996. From Jan. 1982 to March 1991, he has worked with Lanzhou university of China on RF & Microwave Engineering. Before he joined Nanyang Technological University in 1997, he was with Technical University of Nova Scotia, Canada. Now, he is a Professor of the University of Electronic Science and Technology of China. His research interests are: RFIC designs for wireless applications; RF characterization and modeling of semiconductor devices; RF interconnects and packaging; SoC and Applications; EMC/EMI in RFICs. He has published more than 150 technical papers and two books in above mentioned areas. He holds 6 patents in CMOS RFICs. He is now Associate Editor for IEEE Microwave and Wireless Components Letters. Kiat-Seng Yeo received his B.E. (Hons.) (Elect) in 1993, and Ph.D. (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore as a Lecturer in 1996, and became an Assistant Professor and an Associate Professor in 1999 and 2002, respectively. Professor Yeo provides consulting to statutory boards and multinational corporations in the areas of semiconductor devices and electronic circuit design. He has been extensively involved in the modeling and fabrication of small MOS/Bipolar integrated technologies for the last ten years. His research interests also include the design of new circuits and systems (based on scaled technologies) for low-voltage low-power applications; radio frequency integrated circuit (RF IC) design; integrated circuit design of BiCMOS/CMOS multiple-valued logic circuits, domino logic, and memories; and device characterization of deep submicrometer MOSFETs. Manh-Anh Do obtained his B.E. (Hons) (Elect.) in 1973, and Ph.D. (Elect. Eng.) in 1977 both from University of Canterbury, New Zealand. Between 1977 and 1989, he held various positions including: R & D engineer and production manager at Radio Engineering Ltd., research scientist at Fisheries Research Centre, New Zealand, and senior lecturer at National University of Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore as a senior lecturer in 1989, and obtained the Associate Professorship in 1996 and the Professorship in 2001. He has been a consultant for many projects in the Singapore electronic industry, and was the principal consultant for the design, testing and implementation of the $200 million Electronic Road Pricing (ERP) island-wide project in Singapore, from 1990 to 2001. His current research is on digital and mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. Before that, he specialsed in sonar designing, biomedical engineering and signal processing. Since 1995, he has been Head of Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE, UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

Performance Simulation of a Microwave Micro-Electromechanical System Shunt Switch Using Chatoyant

In this paper we demonstrate the capabilities of our mixed-signal, multi-domain system level simulation tool, Chatoyant, to model and simulate an RF MEMS shunt switch. We verify our mechanical simulations and analysis by comparison to results from commercial simulation packages, ANSYS and CoventorWare. We show that our modeling accuracy and simulation speed are comparable to these commercial tools for specific analysis. We conclude by showing the unique capabilities of a system tool based on a modular hierarchal approach that allows one to model not only the individual components of the system but also the subtle interactions resulting in specific system behaviors.Michael Bails received his B.A. in Economics from the University of Vermont in 1995 and a B.S. in Electrical Engineering from the University of Pittsburgh in 2002 (cum laude). He worked as an undergraduate researcher in optical MEMS for Benchmark Photonics, a Pittsburgh-based start-up company from 2001 to 2002. Mr. Bails is currently pursuing his M.S. in the Department of Electrical and Computer Engineering at the University of Pittsburgh, where he is a recipient of the Rath Fellowship. His interests are in MEMS modeling with an emphasis on statistical process variations. Mr. Bails is a student member of IEEE.José A. Martínez is an Electrical Engineering Ph.D. student at the University of Pittsburgh. He received his MS from the University of Pittsburgh (2000) in Electrical Engineering. He received the BS (magna cum laude) in Electrical Engineering from the Universidad de Oriente (UDO), Venezuela, in 1993. Mr. Martínez was granted the José Feliz Rivas’ medal for high academic achievement by the Venezuelan government (1993), and scholarships by the Venezuelan Fundayacucho Society (1993) and CONICIT-UDO (1994) institution. Since 1997 he has been working in the Optoelectronic computing group at the University of Pittsburgh. His research interests include behavioral simulation, reduction order techniques, modeling of MEMs and OMEMs, CAD, VLSI and computer architecture. Mr. Martínez is a member of IEEE/LEOS, and OSA.Steven P. Levitan is the John A. Jurenko Professor of Computer Engineering in the Department of Electrical and Computer Engineering. He received the B.S. degree from Case Western Reserve University in 1972. From 1972 to 1977 he worked for Xylogic Systems designing hardware for computerized text processing systems. He received his M.S. and Ph.D. in Computer Science from the University of Massachusetts, Amherst. During that time he also worked for Digital Equipment Corporation, and Viewlogic Systems, as a consultant in HDL simulation and synthesis. He was an Assistant Professor from 1984 to 1986 in the Electrical and Computer Engineering Department at the University of Massachusetts. In 1987, Dr. Levitan joined the Electrical Engineering faculty at the University of Pittsburgh where he holds a joint appointment in the Department of Computer Science. He is Past Chair of the ACM Special Interest Group on Design Automation (SIGDA). He was awarded the ACM/SIGDA Distinguished Service Award for over a decade of service to ACM/SIGDA and the EDA Industry in 2002. He is on the technical advisory board for The Technology Collaborative. He is a senior member of the IEEE/Computer Society and a member of the Optical Society of America, the Association for Computing Machinery, and the International Society for Optical Engineering. He is a member of the ACM/IEEE Design Automation Conference Executive Committee.Jason Boles received the B.S. degree in computer engineering from the University of Pittsburgh, Pittsburgh, PA, in 2001, where he is currently pursuing the M.S. degree in electrical engineering. His research interests include hardware acceleration techniques for simulation, system level modeling, computer-aided design (CAD), as well as systems-on-chip design and verification. Mr. Boles is a student member of IEEE.Ilya V. Avdeev is currently with ANSYS, Inc (Canonsburg, PA). He received his B.S. and M.S. degrees both in mechanical engineering from St. Petersburg State Polytechnical University (Russia) in 1997 and 1999 respectively. He received his Ph.D. in mechanical engineering from the University of Pittsburgh in 2003. His dissertation was on modeling strongly-coupled MEMS. He has been an inaugural John Swanson Doctoral Fellow and was awarded numerous scholarships and personal grants during his undergraduate and graduate studies. His research interests include mathematical modeling of coupled-field effects, new finite element techniques and methods, design and simulation of MEMS/NEMS, and acoustics. He is a member of ASME and IEEE.Michael R. Lovell is the Associate Dean for Research and an Associate Professor of Industrial and Mechanical Engineering in the School of Engineering at the University of Pittsburgh. Dr. Lovell received his PhD in Mechanical Engineering in 1994 from the University of Pittsburgh. He joined the Mechanical Engineering Department at Pittsburgh in January of 2000 after three years of service as an Assistant Professor at the University of Kentucky and four years of service as a senior development engineer at ANSYS Inc. Professor Lovell is a W. K. Whiteford Endowed Faculty Fellow, has served as the Executive Director of the Swanson Center for Product Innovation since May of 2000, and has been the Director of the Swanson Institute for Technical Excellence since September of 2002. Among his accomplishments, Professor Lovell is a recipient of the NSF CAREER award (1997), the SME Outstanding Young Manufacturing Engineer Award (1999), and won the FAG Outstanding International Publication on Bearings (1998). Dr. Lovell’s primary research interests are in the areas of tribology, advanced computation, and micro and nano systems.Donald M. Chiarulli, Professor of Computer Science. Dr. Chiarulli received his BS degree (Physics, 1976) from Louisiana State University, MSc (Computer Science, 1979) from Virginia Polytechnic Institute, and PhD (Computer Science, 1986) from Louisiana State University. He was an Instructor/Research Associate at LSU from 1979 to 1986, and has been at the University of Pittsburgh since 1986. Dr. Chiarulli’s research interests are in photonic and optoelectronic computing systems architecture. Dr Chiarulli’s research has been recognized with Best Paper Awards at the International Conference on Neural Networks (ICNN-98) and the Design Automation Conference (DAC-00). He is also the co-inventor on three patents relating to computing systems and optoelectronics. He has served on the technical program committees of numerous conferences for both research and education issues. Dr. Chiarulli serves on the editorial board of the Journal of Parallel and Distributed Systems and is a member of the IEEE. SPIE, and OSA.     

An RF CMOS Q-Enhanced LC Resonator

This paper investigates a Q-enhanced LC resonator implemented with a Q-enhancement circuit based on both active and reactive components. An analytical expression is presented for the Q-enhancement circuit and simulations are compared with measurements on a differential Q-enhanced LC tank operating at 1779–1870 MHz. Sensitive circuits and inaccurate models leads to inaccurate simulations. To improve the accuracy of simulations, S-parameter measurements of components and sub-circuits are included in the simulations whereby an accuracy of 3 MHz in the estimate of the resonator center frequency results. Per Madsenreceived his M.Sc.E.E degree in 1997 from Aalborg University, Denmark. In 2005 he received his Industrial PhD degree, also from Aalborg University. He is currently working with development of reference designs for GSM and UMTS at Texas Instruments Denmark A/S. Jan Hvolgaard Mikkelsenreceived his M.Sc.E.E. degree in 1995 from Aalborg University, Denmark. In 2005 he received his PhD degree, also from Aalborg University. He is currently employed as an Assistant Professor at Aalborg University where he is working as an IC design manager for the large scale RF IC design efforts at Aalborg University. His research interests include both RF and LF CMOS design as well as transceiver architectures. Jens Christian Lindofreceived his M.Sc.E.E. degree in electrical engineering in 1991 from Aalborg University, Denmark, in 1991. He is currently R&D Director at Texas Instruments Denmark A/S, where he is responsible for all HW and SW developed for Texas Instrument's cellular reference designs for GSM, GPRS, EDGE and UMTS. Torben Larsenreceived his M.Sc.E.E. degree in electrical engineering from Aalborg University, Denmark, in 1988, and the Dr. Techn. degree from Aalborg University in 1998. He has been employed as full Professor at Aalborg University since 2001. Dr. Larsen serves as reviewer for IEE, IEEE and Wiley. Areas of specialized research interests include noise theory, nonlinear analysis techniques, RF techniques, RF CMOS technology, and digital modulation techniques.