扩频码跟踪及同步失锁的研究与实现

针对扩频通信系统中的PN码同步问题,在分析扩频码跟踪方法的基础上,讨论了同步失锁问题,给出非相干延迟锁定环的计算公式和降低同步失锁误判的方法,并对其进行Matlab仿真及FPGA硬件调试.结果表明:该同步系统能够很好地跟踪接收端PN码的相位变化,失锁电路能够有效工作,并准确判断出同步失锁状况.     

种子注入式单纵单横电光调Q激光器

基于种子注入技术、干涉法腔模锁定方案以及自滤波非稳腔技术,设计并研制出一套单纵单横电光调Q脉冲激光器系统。该系统输出的基波(波长1064nm)能量达到600mJ,倍频后绿光能量达到300mJ,发散角接近衍射极限,线宽接近傅里叶变换极限,在强气流强振动环境中单纵模的锁定概率为100%。实验观测了种子注入对巨脉冲建立时间、光斑模式以及能量的影响。该系统可应用于受激布里渊散射(SBS)、大视场风洞全息以及光学合成孔径等研究领域。     

基于SPRT的PN码捕获建模及其性能分析

讨论了序列概率比检测(SPRT)在直接序列扩频通信系统PN码捕获中的应用。对失锁和入锁条件下的接收序列和本地PN序列的相关序列进行了建模。对该建模的错误概率和平均样本数目进行了分析并导出了计算公式。分析和仿真结果表明随机序列建模的性能优于零序列建模。     

基于采样点选择和矢量旋转的多载波CDMA定时跟踪方案

针对多载波CDMA系统的特点,该文提出一种基于采样点选择和矢量旋转的全数字定时跟踪方案。该方案充分利用准时路复相关矢量信息,通过矢量旋转得到非相干定时误差检测量,进行定时跟踪调整。理论分析和数值结果表明,该方案较传统的延迟锁定跟踪方案明显降低了实现复杂度,而且性能有所提高。     

国标地面数字电视接收机定时同步算法的改进

提出了一种改进的国标数字电视地面广播接收机定时同步算法。该算法对基于PN序列相关的鉴相算法进行了改进,即对相关值进行预滤波,以检测出定时偏差,并采用全数字锁定环技术实现整个算法。软件仿真表明:在相同的信道环境和相近的环路收敛性能条件下,改进后的算法可以工作在2倍符号速率上,有效地降低了算法的复杂度。同时,通过对预滤波器的设计,可灵活地调节S曲线的形状,以调整算法捕获定时偏差的范围。     

窄带干扰对多载波系统定时同步影响的分析

 S&;C算法是基于数据辅助的常用定时同步算法,该算法仅需要一个训练符号,既可用于定时恢复,也可用于载波频率捕获,额外开销小,广泛应用于多载波通信系统中.一般来说,定时估计的性能会受到干扰(如窄带干扰)的影响.分析了窄带干扰信号对多载波系统定时同步的影响,重点分析了窄带干扰情况下S&;C定时估计器的性能、训练数据的漏警概率和虚警概率.     

频谱分析仪中小数环的一点改进

本文介绍了在AV4033频谱分析仪中小数环的的原理及各部分的功能。为了解决环路工作过程中不稳定,容易失锁的问题,在环路滤波器前端电阻上并联一个补偿电容,并提供了获取电容值的算法。采用该方法后,明显提高了小数环路的增益,促进了环路的捕捉与锁定。     

基于内插的全数字二元鉴相相干延迟锁定环

提出一种基于内插的全数字二元鉴相相干延迟锁定环(C-DDLL),用于直接序列码分多址系统上行链路伪随机码的跟踪,对AWGN、多用户于扰以及非理想内插影响下的环路跟踪性能进行了分析与计算机模拟,最后给出了数值结果及分析。     

窄脉冲相干激光雷达偏频锁定系统实验研究

偏频锁定技术广泛应用于激光的外差探测、激光雷达等方面,具有重要应用价值。介绍了自行设计的适用于窄脉冲激光外差信号的偏频锁定控制系统的工作原理,并进行了偏频锁定实验研究,分析了影响本系统鉴频正确性的因素。结果表明对中心频率为80MHz、脉冲宽度约为40ns的外差信号进行的偏频锁定实验,系统很少失锁,锁定精度为±5MHz。     

数字集群对讲机锁相环失锁问题的研究

数字集群对讲机在使用时会概率性出现锁相环失锁问题，造成对讲机在集群模式下无法注册入网、在直通模式下无法通信、调试模式下不能进行指标测试等问题，必须重启机器才能恢复。针对这一现象，从理论上分析，造成这种干扰的可能是信号完整性问题、锁相环的环路滤波器配置问题、电源完整性问题等。针对可能的原因逐个分析和测试，得出增大电源的滤波电容、并同时增加缓启动电路和软件检测锁相环锁定状态的解决方案，从示波器测试结果分析可以看出，彻底解决了因收发切换时电压跌落造成的锁相环失锁问题，对讲机的稳定可靠性得到了明显改善。     

基于数字匹配滤波器与多径合并的CDMA码跟踪环

PN码跟踪环是DS-CDMA蜂窝移动通信系统的关键技术。本文针对第三代(3G)移动通信系统，着眼于对下行公共导频信道的充分利用，提出了一种基于数字匹配滤波器(DMF)和多径误差合并的全数字式码跟踪环。导频信道的DMF输出，一方面可用于信道估计与多径搜索，另一方面用于提取码定时误差，二者结合可以进行码定时误差的多径RAKE合并。理论推导与仿真结果表明，该跟踪环性能良好，具有较高的实用价值。     

Performance of digital code tracking loops for direct-sequencespread-spectrum signals in mobile radio channels

The performance of first- and second-order non-coherent digital delay lock loops (DDLL) for direct-sequence spread-spectrum (DS-SS) signals is investigated in the mobile radio environment. The mobile radio channel is first characterized by Rayleigh fading and Doppler shift. A closed-form expression for the timing error transition probability density function of the Chapman-Kolmogorov (C-K) equation is proposed. The probability density function of the steady-state timing error for the first- and second-order DDLL is obtained by solving the C-K equation numerically, and the results are confirmed by computer simulations. Furthermore, the mean time to lose lock (MTLL) of the first-order loop is evaluated, and some numerical results and simulation results are reported. Finally, the steady-state timing error and MTLL of the first-order loop for DS-SS signals in the log-normal fading environment are also presented, and the results are compared with those of Rayleigh and AWGN channels     

WCDMA功率控制技术的研究与实现

介绍了功率控制技术的作用和分类,以及宽带码分多址(WCDMA)系统反向闭环功率控制的技术标准和组成部分,分析得出了WCDMA系统反向功率控制实现的定时限制条件.讨论了影响功率控制技术性能的几个关键因素:信扰比(SIR)估计精度、步长选择、功控比特传输错误及功控时延等,并给出了仿真曲线和结果分析.最后给出了WCDMA系统前、反向功率控制技术基于FPGA的实现结构框图和测试结果.     

WCDMA上行链路一种新的参数优化方法

本文在研究了WCDMA上行链路导频信道辅助相干解调的基础上,提出了参数优化的一种新方法.根据给定信噪比下误码概率最小的准则,本文得到了理论上信道估计器最佳的平均长度和导频信道相对数据信道最优的功率比.     

PAM-TH-UWB系统抗UMTS干扰性能分析

分析了UMTS／WCDMA系统所产生的干扰对PAM—IR-UWB系统的影响，推导出了UWB系统在存在UMTS干扰下的误比特率公式，解析分析了UWB发射信号的基本参数与抗UMTS干扰能力之间的关系。数值计算和仿真验证了分析的正确性和UWB系统抗UMTS干扰的能力。     

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

The design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.     

相关衰落信道上WCDMA系统的安全性能分析

对多输入多输出（MIMO）相关衰落信道上宽带码分多址接入（WCDMA）的安全性能进行评估,一种省时高效的解决方案是理论分析法。推导了相关 Nakagami 衰落信道上采用空时分组码和二维瑞克接收机（2D-Rake）的 WCDMA 系统的非零安全容量概率和安全中断概率的精确解析表达式。利用上述表达式,可以快速地评估收发天线数、天线相关系数、Nakagami衰落系数、平均路径衰减系数等参数对WCDMA系统安全性能造成的影响。数值计算和仿真结果相吻合,证明了以上理论分析的正确性。推导了WCDMA系统渐近安全中断概率的解析表达式。结果表明,WCDMA 系统的安全分集增益为主信道各个可分离路径上的分集增益之和,与窃听信道无关;对于恒定多径强度轮廓的同分布Nakagami衰落信道,WCDMA系统的安全分集增益为主信道的收/发天线数、多径个数以及Nakagami衰落系数四者之积。     

Communication systems with PPM signaling

Effect of imperfect slot synchronization between the transmitter and the receiver on optical synchronous code-division multiple-access (CDMA) systems using pulse position modulation as data modulation (PPM/CDMA) is investigated. Optical orthogonal codes (OOC's) are employed as signature sequences, and parallel optic-fiber delay line encoders and correlators are adopted in the transmitters and the receivers, respectively. The upper bound on the bit error probability of PPM/CDMA is derived under the condition that the receiver slot timing shifts from the transmitter timing clock. The bit error probability performance is evaluated for some values of the number of slots per frame, average signal photocount, and the number of simultaneous users. It is shown that as the number of slots per frame increases, the timing offset should be restricted to be smaller to achieve low bit error probability. Further, when the timing offset is small, the improvement of the bit error probability performance with the increase of the number of slots per frame under the photocount per second constraint is shown to be larger than that under the photocount per symbol constraint     

Adjacent-Channel and Quadrature-Channel Interference in Minimum Shift Keying

In this paper we present formulas for the computation of error probability in the presence of quadrature-channel or adjacentchannel interference in addition to intersymbol interference in a minimum shift keying system. The filters in the receiver and transmitter are arbitrary but with a finite number of poles. The effect of phase jitter in the main channel, phase and symbol timing misalignment in the interfering channels, and sampling time jitter is taken into account. The probability of error is averaged over the phase and symbol timing misalignment. Numerical results are presented for Butterworth filters in the receiver and transmitter with two, three, and four poles. Curves of error probability as a function of various variables (signal-to-noise ratio, bandwidth of receiver and transmitter filters, number of poles, channel frequency separation, phase jitter, sampling time, and symbol timing and phase misalignment) are presented. The method of this paper can readily be applied to other filters; hence, it can be used in the design and prediction of the performance of digital communication systems.     

A fast-lock mixed-mode DLL using a 2-b SAR algorithm

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL, and SARDLL, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The measured RMS and peak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, respectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1 LSB (156 ps)