Study of CMOS Process Variation by Multiplexing Analog Characteristics

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.      

Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

Interconnect characterization of X architecture diagonal lines for VLSI design

This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs.     

A novel transmission line characterisation based on measurement data reconfirmation

Due to inherent resonance effects and frequency-variant dielectric properties, it is very difficult to experimentally determine the stable and accurate circuit model parameters of thin film transmission line structures over a broad frequency band. In this article, a new, simple and straightforward frequency-variant transmission line circuit model parameter determination method is presented. Experimental test patterns for high-frequency transmission line characterisations are designed and fabricated using a package process. The S-parameters for the test patterns are measured using a vector network analyzer (VNA) from 100 MHz to 26.5 GHz. The parasitic effects due to contact pads are de-embedded. The frequency-variant complex permittivity and resonance-effect-free transmission line parameters (i.e., the propagation constant and characteristic impedance) are then determined in a broad frequency band.     

Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects

The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.     

单端口声表面波谐振器在片去嵌方法分析

为了准确地设计声表滤波器,需要从参考声表面波(SAW)谐振器的测量值中提取精确的材料参数。测量SAW谐振器时,单个谐振器无法直接进行测试,需要引出传输线并使用GSG或GS探针进行测量,消除传输线影响的去嵌入过程对于SAW谐振器材料参数的准确提取非常重要。该文介绍了几种声表面波谐振器的去嵌入技术,包括Open-Short算法、电磁仿真方法、分段等效电路模型方法、集总参数等效电路法。通过实例验证了几种常用的去嵌方法并对其进行了分析。     

A simple method for on-chip, sub-femto Farad interconnectcapacitance measurement

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

精确区分器件和互连寄生电阻电容的方法研究

随着器件线宽的不断缩小,在集成电路仿真中互连线延迟所占的比重逐渐变大,而MOSFET延迟所占的比重慢慢减小,这就意味着互连的寄生电阻电容对延迟的影响越来越大.研究了如何区分并计算器件部分和互连部分的寄生电阻电容.其中区分本地互连寄生电阻电容和器件电阻电容是关键.以90 nm器件为例,通过提取不同部分的寄生电阻电容,对环形振荡器进行延迟仿真,得到了它们对延迟的影响.通过不同的测试结构达到精确计算器件寄生电阻电容的目的,最终实现了对电路的精确仿真.     

含寄生网络的激光器小信号调制响应模拟新方法

在高速通信中应准确分析激光器高频调制响应需要计及寄生网络的影响。推导了激光器测试系统散射参数与本征响应传输函数之间的关系，提出用激光器散射参数扣除求取激光器本征响应和模拟激光器整体小信号调制响应的新方法。结合激光器的等效电路和速率方程分析，避免了单独测量寄生网络和估计有源区电路参数。对法布里-珀罗型激光器样品测试发现，仿真与实验的结果吻合。这一模拟方法简便快捷，准确性好。     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

动态随机存储器中堆叠电容器结构的互连寄生电容模拟

在高密度比特位动态随机存储器(DRAM)芯片的发展中,随着多层布线与复杂存储单元结构的日渐普遍使用,互连寄生电容对存储器件性能如时延、功耗、噪声等的影响日渐突出,已成为不可忽视的重要因素,对互连寄生电容提取软件提出了紧迫的要求.本文介绍一个基于直接边界元素法的精度高,速度快,并可适应复杂堆叠(stacked)电容器结构的互连寄生电容模拟软件,并通过实例计算,分析DRAM中互连线寄生电容对电路性能的影响.     

Rapid characterization and modeling of pattern-dependent variationin chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

A three-step method for the de-embedding of high-frequencyS-parameter measurements

The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (⩾10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding     

Fabrication techniques for a novel three-dimensional monolithicintegrated circuit transmission line in silicon

A novel integrated circuit transmission line, trench waveguide, has been developed for high frequency/high speed applications. The three-dimensional structure is suitable as a low impedance interconnect. The fabrication process developed uses special wet etch, and angle evaporation techniques. Measurements on large-scale models of the device yielded impedances as low as 12 Ω     

Computer-Aided Small-Signal Characterization of IMPATT Diodes

This paper is a discussion of IMPATT wafer small-signal characteristics in the frequency range of 2.0-8.0 GHz. These characteristics have been obtained by computer conversion of reflection phase-gain data. The data handling technique which allows establishment of the desired reference plane and the reduction of the admittance data into the desired equivalent circuit is presented. A calibration procedure using reference impedances consistent with the diode geometry is discussed. The validity of the microwave measurement technique and the data handling process is demonstrated by comparison of the values of junction capacitance determined at microwave frequencies with junction capacitance measurements at 30 MHz. Representative plots are given for wafer conductance and susceptance as a function of frequency with current density as a parameter. In addition, typical values obtained for the circuit elements are presented. These data illustrate the capability of determining package inductance, series resistance as a function of bias voltage, and, with the diode in avalanche, the parallel G, L, and C of the wafer admittance. The diode equivalent circuit was studied as a function of current density to compare results with the existing analytical small-signal theories. This procedure permits the separation of the wafer elements from the parasitic elements of the package. Data obtained from these measurements are extremely useful for ascertaining wafer design parameters and assisting in circuit design.