Order statistics from a logistic distribution and applications to survival and reliability analysis

Joint moments involving arbitrary powers of order statistics are the main concern. Consider order statistics u/sub 1/ /spl les/ u/sub 2/ /spl les/ /spl middot//spl middot//spl middot/ /spl les/ u/sub k/ coming from a simple random sample of size n from a real continuous population where u/sub 1/ = x/sub r(1):n/ is order-statistic #r/sub 1/, u/sub 2/ = x/sub r(1)+r(2):n/ is order statistic #(r/sub 1/ + r/sub 2/), et al., and u/sub k/ = x/sub r(1)+/spl middot//spl middot//spl middot/+r(k):n/ is order statistic #(r/sub 1/ +/spl middot//spl middot//spl middot/+ r/sub k/). Product moments are examined of the type E[u/sub 1//sup /spl alpha/(1)/ /spl middot/ u/sub 2//sup /spl alpha/(2)//sub /spl middot/ /spl middot//spl middot//spl middot//spl middot//u/sub k//sup /spl alpha/(k)/] where /spl alpha//sub 1/, ..., /spl alpha//sub k/ are arbitrary quantities that might be complex numbers, and E[/spl middot/] denotes the s-expected value. Some explicit evaluations are considered for a logistic population. Detailed evaluations of all integer moments of u/sub 1/ and recurrence relations, recurring only on the order of the moments, are given. Connections to survival functions in survival analysis, hazard functions in reliability situations, real type-1, type-2 /spl beta/ and Dirichlet distributions are also examined. Arbitrary product moments for the survival functions are evaluated. Very general results are obtained which can be used in many problems in various areas.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.     

The analysis of dark signals in the CMOS APS imagers from the characterization of test structures

The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD. The dark currents from the transfer gate can be effectively reduced by the tail of p/sup +/ region on the surface of the transfer gate, and those from the floating diffusion (FD) node were estimated to be negligible in the normal operational mode. However, because of the enhanced thermal generation velocity caused by the severe process-induced damages, the FD node was considered as the main source of increased dark currents in the single frame capture mode. The characteristics of quantized dark currents causing the white pixels in the CMOS APS were examined using the dark current spectroscopy method. Three distinct deep-level bulk traps have been identified with the location in the silicon bandgap at |E/sub t/-E/sub i/|/spl sim/0.020 (eV), |E/sub t/-E/sub i/|/spl sim/0.082 (eV), and |E/sub t/-E/sub i/|/spl sim/0.058 (eV), and capture cross sections of 7.80/spl times/10/sup -15/ cm/sup 2/, 1.83/spl times/10/sup -13/ cm/sup 2/, and 1.46/spl times/10/sup -13/ cm/sup 2/ respectively.     

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

A 4.15 kV 9.07-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC Schottky-barrier diode using Mo contact annealed at high temperature

In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/.     

Room-temperature InAsSb photovoltaic detectors for mid-infrared applications

Novel noncryogenic InAsSb photovoltaic detectors grown by molecular beam epitaxy are proposed and demonstrated. The quaternary alloy In/sub 0.88/Al/sub 0.12/As/sub 0.80/Sb/sub 0.20/ is introduced as a wide bandgap barrier layer lattice matched to the GaSb substrate. The valence band edge of In/sub 0.88/Al/sub 0.12/As/sub 0.80/Sb/sub 0.20/ nearly matches with InAs/sub 0.91/Sb/sub 0.09/, leading to more efficient transport of photogenerated holes. The resulting mid-infrared photovoltaic detector exhibits a 50% cutoff wavelength of 4.31 /spl mu/m and a peak responsivity of 0.84 A/W at room temperature. High Johnson-noise-limited detectivity (D/sup */) of 2.6/spl times/10/sup 9/ cm/spl middot/Hz/sup 1/2//W at 4.0 /spl mu/m, and 4.2/spl times/10/sup 10/ cm/spl middot/Hz/sup 1/2//W at 3.7 /spl mu/m are achieved at 300 K and 230 K, respectively.     

1677 V, 5.7 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC BJTs

This letter reports the development of a high-performance power 4H-SiC bipolar junction transistor (BJT) with, simultaneously, a high blocking voltage and a low specific on-resistance (R/spl I.bar//sub ON/). A single BJT cell with an active area of 0.61 mm/sup 2/ achieves an open base collector-to-emitter blocking voltage (V/sub ceo/) of 1677 V and conducts up to 3.2 A at a forward voltage drop of V/sub CE/=3.0 V, corresponding to a low R/spl I.bar//sub ON/ of 5.7 m/spl Omega//spl middot/cm/sup 2/ up to Jc=525 A/cm/sup 2/ and a record high value of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ of 493 MW/cm/sup 2/.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

Semi-empirical model of the ensemble-averaged differential Mueller matrix for microwave backscattering from bare soil surfaces

A semi-empirical model of the ensemble-averaged differential Mueller matrix for microwave backscattering from bare soil surfaces is presented. Based on existing scattering models and data sets measured by polarimetric scatterometers and the JPL AirSAR, the parameters of the co-polarized phase-difference probability density function, namely the degree of correlation /spl alpha/ and the co-polarized phase-difference /spl sigmav/, in addition to the backscattering coefficients /spl sigma//sub /spl nu//spl nu///sup 0/,/spl sigma//sub hh//sup 0/ and /spl sigma//sub /spl nu/h//sup 0/, are modeled empirically in terms of the volumetric soil moisture content m/sub /spl nu// and the surface roughness parameters ks and kl, where k=2/spl pi/f/c, s is the rms height and l is the correlation length. Consequently, the ensemble-averaged differential Mueller matrix (or the differential Stokes scattering operator) is specified completely by /spl sigma//sub /spl nu//spl nu///sup 0/,/spl sigma//sub hh//sup 0/,/spl sigma//sub /spl nu/h//sup 0/,/spl alpha/, and /spl zeta/.     

High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification

This letter presents technologies to fabricate ultralow-temperature (< 150 /spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al/sub 2/O/sub 3/ grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm/sup 2//V /spl middot/ s (nMOS) and 42 cm/sup 2//V /spl middot/ s (pMOS), on/off current ratio of 4.20 /spl times/ 10/sup 6/ (nMOS) and 5.7 /spl times/ 10/sup 5/ (pMOS), small V/sub th/ of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS).     

Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 /spl mu/m /spl sim/4.9/spl times/10/sup 14/ cm/sup -3/-doped drift layer. Blocking voltages (V/sub B/) of 10 kV to 11 kV have been measured. The best specific on-resistance (R/sub SP/_/sub ON/) normalized to source active area has been determined to be 130 m/spl Omega//spl middot/cm/sup 2/. Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 m/spl Omega//spl middot/cm/sup 2/ if it is scaled up substantially in size.     

Compression mappings on primitive sequences over Z/(p/sup e/)

Let Z/(p/sup e/) be the integer residue ring with odd prime p/spl ges/5 and integer e/spl ges/2. For a sequence a_ over Z/(p/sup e/), there is a unique p-adic expansion a_=a_/sub 0/+a_/spl middot/p+...+a_/sub e-1//spl middot/p/sup e-1/, where each a_/sub i/ is a sequence over {0,1,...,p-1}, and can be regarded as a sequence over the finite field GF(p) naturally. Let f(x) be a primitive polynomial over Z/(p/sup e/), and G'(f(x),p/sup e/) the set of all primitive sequences generated by f(x) over Z/(p/sup e/). Set /spl phi//sub e-1/ (x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,1/(x/sub 0/, x/sub 1/,...,x/sub e-2/) /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,2/(x/sub 0/,x/sub 1/,...,x/sub e-2/) where /spl eta//sub e-2,1/ and /spl eta//sub e-2,2/ are arbitrary functions of e-1 variables over GF(p) and 2/spl les/k/spl les/p-1. Then the compression mapping /spl phi//sub e-1/:{G'(f(x),p/sup e/) /spl rarr/ GF(p)/sup /spl infin// a_ /spl rarr/ /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) is injective, that is, a_ = b_ if and only if /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl phi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/). Furthermore, if f(x) is a strongly primitive polynomial over Z/(p/sup e/), then /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl psi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) if and only if a_ = b_ and /spl phi//sub e-1/(x/sub 0/,...,x/sub e-1/) = /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/).     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

Highly reliable GaN-based light-emitting diodes formed by p-In/sub 0.1/Ga/sub 0.9/N-ITO structure

Indium-tin-oxide (ITO) is deposited as a transparent current spreading layer of GaN-based light-emitting diodes (LEDs). To reduce the interfacial Schottky barrier height, a thin p-In/sub 0.1/Ga/sub 0.9/N layer is grown as an intermediate between ITO and p-GaN. The contact resistivity around 2.6/spl times/10/sup -2/ /spl Omega//spl middot/cm/sup 2/ results in a moderately high forward voltage LED of 3.43 V operated at 20 mA. However, the external quantum efficiency and power efficiency are enhanced by 46% and 36%, respectively, in comparison with the conventional Ni-Au contact LEDs. In the life test, the power degradation of the p-In/sub 0.1/Ga/sub 0.9/N-ITO contact samples also exhibits a lower value than that of the conventional ones.     

First fully integrated 2-D array of single-photon detectors in standard CMOS technology

A two-dimensional (2-D) array (4 by 8) of single-photon avalanche diodes integrated in an industrial complementary metal-oxide-semiconductor (CMOS) process is presented. Each pixel combines a photodiode biased above its breakdown voltage in the so-called Geiger mode, a quenching resistor, and a simple comparator. The pitch between the pixels is 75 /spl mu/m and the diameter of each pixel is 6.4 /spl mu/m. The full integration allows reducing the number of charge carriers in a Geiger pulse. The electroluminescence responsible for optical crosstalks between pixels is then reduced leading to a negligible optical crosstalk probability. Thanks to the cleanness of the fabrication process, no afterpulsing effects are noticed. At room temperature, most of the pixels exhibit a dark-count rate of about 50 Hz. The detection probability is almost identical for all 32 pixels of the array with relative variation in the range of a few percents. This letter demonstrates the feasibility of an array of single-photon detectors sensitive in the visible part of the spectrum. Besides low production costs and compactness, an undeniable benefit lies in the potential to easily modify the design to fit a specific application. Furthermore, the CMOS integration opens the way to on-chip data processing.     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.