Low Distortion and Swing Suppression Sigma-Delta Modulator with Extended Dynamic Range Scheme

This work presents a new low distortion and swing suppression second order sigma-delta modulator with extended dynamic range scheme. The proposed modulator is based on the dual-quantizer architecture and can effectively extend the dynamic range by only adding two simple digital filters in the digital circuit. The techniques of low distortion and swing suppression integrator designs are also employed in the new architecture. Accordingly, this new architecture can improve the circuitry nonlinearity, and the in-band noise can be significantly suppressed to achieve a high resolution in mid or wide bandwidth applications. A second order SDM for Bluetooth application with bandwidth of 500 KHz and sampling frequency of 40 MHz was designed and implemented. The peak SNDR of the experimental SDM is 78 dB.     

A wideband CMOS sigma-delta modulator with incremental dataweighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm². Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A dual-mode complex filter for GNSS receivers with frequency tuning

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18 fxm CMOS process. This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz. A fully differential OTA with source degeneration is used to provide sufficient linearity. Furthermore, a ring CCO based frequency tuning scheme is proposed to reduce frequency variation. The measured results show that in narrow-band mode the image rejection ratio (IMRR) is 35 dB, the filter dissipates 0.8 mA from the 1.8 V power supply, and the out-of-band rejection is 50 dB at 6 MHz offset. In wide-band mode, IMRR is 28 dB and the filter dissipates 3.2 mA. The frequency tuning error is less than ±2%.     

一种用于分数频率合成器的3阶单环ΣΔ调制器

分析了无线通信分数分频频率合成器的关键模块ΣΔ调制器(SDM)的设计方法,并提出了一种系数能用移位产生的简单高效的单环3阶3位量化SDM结构。该电路采用标准0.18μm CM O S工艺实现,电源电压1.8 V,内部使用24位总线,在工作频率为16MH z时,可到达的频率分辨率为8 H z,结果表明它的带外噪声平坦、输出位宽窄,优于同阶级联ΣΔ结构。     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

Broadband UHF RFID tag antenna with a pair of U slots mountable on metallic objects

A broadband ultra-high frequency radio frequency identification (UHF RFID) tag patch antenna with a pair of U slots is presented. By embedding a pair of U slots on the patch, a new resonant mode adjacent to the origin mode is excited and a broadband characteristic is achieved. The measured half-power bandwidth of the proposed antenna is 133 MHz and it covers all UHF RFID frequency bands. Measurement results show that the proposed antenna can work on metallic objects of different sizes in both North America and Europe bands.     

一种用于谐波倍增回旋放大器的耦合腔互作用电路

该文提出了一种用于回旋管放大器的新型耦合腔互作用电路模型。基于Ansoft HFSS高频计算软件,分析计算了矩形波导TE□10模输入,圆波导TE○01模输出模式转换系数随几何参数和工作频率的变化关系,讨论了结构变化对模式选择和抑制的作用。HFSS的模拟计算结果表明,对TE□10到TE○01转换,TE○01模能够稳定工作,且能量转换效率最大可以大于97%,－3dB带宽最大可以大于327MHz,是谐波倍增回旋行波放大器的一种可选输入耦合结构。     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

Design and Analysis of Tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) with Enhanced Performance and Its Application in Filters

This paper proposes a high performance tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) where transconductance of VDIBA is enhanced by using programmable positive feedback technique and bandwidth is enhanced by using resistive compensation technique. The enhanced performance of proposed VDIBA is demonstrated by presenting detailed frequency analysis. Furthermore, it is verified that transconductance of proposed VDIBA can be enhanced up to 10.6 mS at tuning current (Ic) of 100 µA. Moreover, resistive compensation technique enhance bandwidth of propose circuit up to 263 MHz. To illustrate the effectiveness of proposed circuit, voltage mode universal biquad filter is designed as an application example. The pole frequency of proposed filter is tunable in range of 10.5–83.4 MHz. The proposed VDIBA and its filter applications are designed and simulated using TSMC 0.18 µm CMOS technology in Cadence virtuoso schematic composer at ± 0.6 V supply voltage.     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.     

70-MHz IF 10-MHz bandwidth bandpass \Upsigma\Updelta modulator for WCDMA applications

A MASH bandpass $\Upsigma\Updelta$ modulator for wide-band code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10?MHz centered around an intermediate frequency (IF) of 70.5?MHz. Two two-path second-order bandpass $\Upsigma\Updelta$ modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The proposed circuit, fabricated with a 0.18???m CMOS technology, uses a sampling frequency of 180?MHz to obtain a resolution of about 12?bits in the 10?MHz bandwidth around the IF. The measured modulator power consumption is 95?mW with a supply voltage of 1.8?V. The achieved figure-of-merit (FoM _BP ) is 0.37?pJ/conversion-level.     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

Electronic mode stirring for reverberation chambers

A modal analysis and a uniform-field approximation are presented for the fields in an idealized two-dimensional, rectangular cavity excited by an electric line source. The model is used to evaluate the effectiveness of frequency stirring, an alternative to mechanical stirring in reverberation chamber immunity measurements. Numerical results indicate that good field uniformity (standard deviation less than 1 dB) can be obtained with a bandwidth of 10 MHz at a center frequency of 4 GHz. The bandwidth requirement is determined primarily by the number of modes excited, and higher frequencies can achieve the same field uniformity with a smaller bandwidth because of the higher mode density. Cavity excitation by two single-frequency sources is also analyzed     

基于数/模混合预失真技术的功放线性化北大核心CSCD

随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。     

A broadband circularly polarized antenna of square-ring patch for UHF RFID reader applications

A circularly polarized, broad bandwidth, square-ring patch antenna for radio-frequency identification (RFID) is proposed. The antenna has a dimension of 100 × 100 × 22.9 mm³. By using a Wilkinson power divider and a patch-antenna structure, a measured 3-dB axial-ratio bandwidth of approximately 140 MHz (16.47%), an impedance bandwidth of 136 MHz (15.81%), and a measured peak gain of approximately 6.8 dBic are being achieved. The operating band of the proposed antenna is suitable for China (840–846 MHz), Europe (865–868 MHz) and the United States (902–928 MHz) ultra-high frequency (UHF) RFID applications.     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.