VVMOS功率晶体管的负阻击穿

VVMOS晶体管是一种开有V形槽的垂直沟道高频功率MOS场效应器件,它的一个主要优点是与其它MOS器件一样不会发生二次击穿,然而近来一些作者报道MOS器件有负阻击穿效应,而这种负阻击穿效应也会引起二次击穿,导致器件烧毁。我们在测量自制的VVMOS晶体管时,也观察到了负阻击穿,经过研究,提出了纵向寄生npn双极晶体管的VVMOS晶体管负阻击穿模型,在此基础上还提出了几种抑制负阻击穿效应的方法,在采用了这些方法后,负阻击穿效应被减弱,甚至被消除,从而证实了所提出的VVMOS晶体管负阻击穿模型。     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFET's is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFET's.     

The COMFET—A new high conductance MOS-gated device

A new MOS gate-controlled power switch with a very low on-resistance is described. The fabrication process is similar to that of an n-channel power MOSFET but employs an n^--epitaxial layer grown on a p⁺substrate. In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance. For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Simulating single-event burnout of n-channel power MOSFET's

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs     

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs[MESFETs read MOSFETs]

A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFET's which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G _m and current drive at 1.5× higher than the MOSFET's normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions     

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.     

Use of zone-melting recrystallization to fabricate a three-dimensional structure incorporating power bipolar and field-effect transistors

Three-dimensional (3-D) structures have been fabricated incorporating power bipolar transistors in a Si substrate and metal-oxide-semiconductor field-effect transistors (MOSFET's) in an overlying silicon-on-insulator (SOI) film that was zone-melting recrystallized with a graphite strip heater. Both N-P-N and P-N-P bipolar transistors were used. The N-P-N devices exhibited no significant change in transistor characteristics after zone-melting recrystallization (ZMR), while the P-N-P devices showed a substantial reduction in breakdown voltage. The MOSFET's exhibited electron mobilities comparable to those in similar devices fabricated in single-crystal Si wafers. The bipolar transistor yield is approximately 90 percent. The unusually high device quality and yield for 3-D structures obtained by the ZMR technique demonstrates the feasibility of fabricating monolithic structures incorporating both logic functions and relatively high-current high-voltage power switches.     

A three-terminal intelligent power MOSFET with built-in reversebattery protection for automotive applications

An intelligent power MOSFET with built-in reverse battery protection, which is important for automotive power switches, has been developed. The protection is accomplished by integrating an additional power MOSFET in series with a power MOSFET and the control circuit of the additional power MOSFET. The reverse battery protection is achieved without using external control signals. The positive drain breakdown voltage for the proposed MOSFET is 71 V and the negative drain current at a drain voltage of -16 V is only -750 μA. The on-state resistance is 170 mΩ. This new intelligent power MOSFET can replace the conventional three-terminal power MOSFET's used in automotive applications     

Study of the extended p+ dual source structure foreliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p⁺ dual source SOI MOSFET are reported. It is shown that the presence of the extended p ⁺ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p⁺ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's     

Optimization of nonplanar power MOS transistors

Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm²active area. With a high channel width packing density design and 2.5-mm²active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratioR_{off}/R_{on}of approximately 10¹⁰for a 20-V variation in gate-to-source voltage.     

γ—Radiation effects on MOSFET's fabricated with NMOS Submicrometer technology

In this letter, we report γ-radiation effects on MOSFET's fabricated with NMOS submicrometer technology. We have investigated the radiation sensitivity of n-channel MOSFET's with Leffvarying from 6 to 0.3 µm and with a gate oxide thickness of 250 Å. We observed that, for radiation doses ≤ 10⁴rad's, the threshold voltage shift is less than 75 mV and this shift is independent of the device geometry (even for Leff= 0.3 µm). A comparision has also been made between TaSi2gate MOSFET's and poly-gate MOSFET's. The deposition of TaSi2on poly/oxide/silicon structure does not decrease the radiation sensitivity of these MOSFET's. We have also compared MOSFET's fabricated with X-ray lithography and optical lithography. The X-ray lithography does not have a significant effect on the radiation sensitivity of these MOSFET's.     

Numerical analysis of short-circuit safe operating area forp-channel and n-channel IGBTs

The mechanisms of destructive failure of an insulated gate bipolar transistor (IGBT) at short-circuit state are discussed. Results from two-dimensional numerical simulation of p-channel and n-channel IGBTs are presented. It is found that there are two types of destructive failure mechanisms: a secondary breakdown and a latchup. Which type is dominant in p-channel and n-channel IGBTs depends on an absolute value of forward voltage |V_CE|. At moderately low |V _CE|, the p-channel IGBT is destroyed by secondary breakdown, and the n-channel IGBT, by latchup. This is due to the difference of a type of flowing carrier crossing a base-collector junction of wide base transistor and ionization rates of electrons and holes     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

An n-channel MOSFET with Schottky source and drain

An n-channel MOSFET with Schottky source and drain (SBMOSFET) has been successfully fabricated using tantalum for the Schottky electrodes. For long gatelengths (100 µm), there are no significant differences in the characteristics of these SBMOSFET's compared to those of conventional MOSFET's. A significant current reduction is observed in SBMOSFET's having 10-µm gatelengths, however, due to the barrier between source and channel. In spite of the substantial barrier height (0.7 V) between tantalum and p-silicon, still larger barriers and a reduction in the isolation gap between source and channel are desirable for high-drive-high-speed device operation.     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel