新颖的双栅高压MOS集成电路

本文分析了高压MOS器件中的负阻效应,描述了负阻击穿机理的物理模型,提出了一种新颖的双栅高压MOS结构,有效地抑制了负阻击穿,从而提高了器件的可靠性.     

金槽BSIT：一种新型静态感应晶体管

功率型静态感应晶体管BSIT是一种高频、高速的功率场控制器件,它既具有功率MOS管一样高的开关速度,又具有双极晶体管一样低的导通压降。它不会发生功率MOS管那样的静电击窗,也不会发生双极晶体管那样的二次击穿。它具有很大的过电流能力,有很宽的安全工作区,是一种非常优良的功率开关器件。     

关于VDMOSFET二次击穿现象的分析和研究

在PDP驱动电路中的高压功率器件大量采用了VDMOS器件,由二次击穿引起的器件损坏不容忽视。本文讨论了双极晶体管和功率晶体管VDMOS二次击穿的现象,着重分析了功率晶体管VDMOS二次击穿的原因,并提出了改善其二次击穿现象的最佳设计参数及最优准则：基于寄生晶体管基区结深和浓度优化的方法。同时用器件仿真软件MEDICI模拟了各参数对功率晶体管VDNMOS二次击穿的影响。给出了仿真结果。     

4H-SiC功率MESFET的击穿特性

研究了4H-SiC MESFET器件的电学击穿特性和热学稳定性.建立了金属半导体场效应晶体管器件二维数值模型,分析了雪崩碰撞离化效应、隧穿效应和热效应在器件击穿中的作用.综合考虑了栅极偏置、自热效应等因素对击穿的影响.采用准静态方法,求解瞬态偏微分方程组,分析了器件的耐热耐压性能和可靠性.     

关于V形槽的刻蚀技术和VVMOS晶体管的“栅穿”控制

VVMOSFET是一种新型的场效应器件。它具有高输入阻抗、高电流增益、高开关速度、无二次击穿等一系列优点。国内外的工作已经表明:在高频大功率,特别是高速大电流的应用场合,VVMOSFET比双极型器件具有更大的优越性。 本文结合400MHz、2.5W 的VVMOS高频高速功率晶体管的研制工作,对V形槽的刻蚀技术和“栅穿”控制这两个关键工艺作探讨。     

4H-SiC功率MESFET的击穿特性

研究了4 H- Si C MESFET器件的电学击穿特性和热学稳定性.建立了金属半导体场效应晶体管器件二维数值模型,分析了雪崩碰撞离化效应、隧穿效应和热效应在器件击穿中的作用.综合考虑了栅极偏置、自热效应等因素对击穿的影响.采用准静态方法,求解瞬态偏微分方程组,分析了器件的耐热耐压性能和可靠性     

VDMOSFET二次击穿效应的研究

在PDP驱动电路中高压功率器件大量采用了VDMOS器件，由二次击穿引起的器件损坏不容忽视。本文讨论了双极晶体管和功率晶体管VDMOS二次击穿的现象，并着重分析了功率晶体管VDMOS二次击穿的原因，提出了改善其二次击穿现象的措施。用器件仿真软件MEDICI模拟了各参数因素对功率晶体管VDMOS二次击穿的影响。     

新型无负阻击穿双栅型高压NMOS集成器件

本文讨论了高压NMOS集成器件中负阻击穿观象的机理。给出了发生负阻击穿的判定条件,建立了模型。 采用与目前国际上先进的主流工艺——n阱硅栅等平面CMOS工艺完全兼容的工艺流程,且无需增加任何工艺步骤,研制成一种新型的无负阻击穿的双栅型高压NMCS器件。在栅压为0～10V时,其漏源击穿电压大于300V,最大饱和电流大于0.3mA/单位宽长比(栅压为10V时),导通电阻为44kΩ·单位宽长比(栅压为10V时),具有广泛的应用价值。     

High-k材料MOS器件的PISCES-II模拟

High-k材料是指介电常数k高于SiO2的材料。使用high-k材料做栅绝缘层,是减小MOS器件栅绝缘层直接隧道击穿(DirectTunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES-II中添加了模拟以high-k材料为栅绝缘层的MOS器件模型,并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较,成功地验证了所加high-k材料MOS器件模型的正确性。改进后的PISCES-II程序,可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。     

功率MOS器件

本文介绍新近功率MOS场效应晶体管的主要结构和电学性能。为了提高MOS晶体管的电流和电压容量,首先得论述一些基本概念;然后介绍迄今为止最有希望的功率MOS结构,即V·MOS和VD·MOS晶体管中所使用的方法。 接着,我们叙述这些器件的电学性能,即阈值电压、电压—电流特性、欧姆(电阻)特性、饱和及准饱和范围,一次和二次击穿、安全工作区。还讨论了某些动态特性。最后,分析了功率MOS场效应晶体管的基本限制之一,即导通电阻与电压控制能力间的权衡;并提供了某些与其它功率器件的比较数据。     

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p^-on p⁺epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.     

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.     

Numerical analysis of short-circuit safe operating area forp-channel and n-channel IGBTs

The mechanisms of destructive failure of an insulated gate bipolar transistor (IGBT) at short-circuit state are discussed. Results from two-dimensional numerical simulation of p-channel and n-channel IGBTs are presented. It is found that there are two types of destructive failure mechanisms: a secondary breakdown and a latchup. Which type is dominant in p-channel and n-channel IGBTs depends on an absolute value of forward voltage |V_CE|. At moderately low |V _CE|, the p-channel IGBT is destroyed by secondary breakdown, and the n-channel IGBT, by latchup. This is due to the difference of a type of flowing carrier crossing a base-collector junction of wide base transistor and ionization rates of electrons and holes     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

Breakdown behavior of GaAs/AlGaAs HBTs

Avalanche breakdown behavior at the collector junction of the GaAs/AlGaAs HBT (heterojunction bipolar transistor) has been studied. Junction breakdown characteristics displaying hard breakdown, soft breakdown, and negative resistance breakdown behavior were observed and are interpreted by analysis of localized microplasma effects, uniform microplasma-free behavior, and associated current gain measurements. Light emission from the collector-base junction of the GaAs/AlGaAs HBT was observed and used to investigate breakdown uniformity. Using a simple punchthrough breakdown model, the theoretical breakdown curves at different collector doping concentrations and thicknesses were computed and found to be in agreement with maximum breakdown voltages measured from devices displaying the most uniform junction breakdown. The serious current gain degradation of GaAs/AlGaAs HBTs at low current densities was analyzed in connection with the measurement of a large collector-emitter breakdown voltage. The unexpected functional relationship between the collector-emitter breakdown voltage and collector-base breakdown voltage is explained by the absence of a hole-feedback effect for devices not exhibiting transistor action     

一种带有极化掺杂电流阻挡层的垂直AlGaN/GaN HFET

针对传统垂直GaN基异质结场效应晶体管中,由于GaN电流阻挡层内p型杂质激活率低而导致的漏电问题,提出了一种使用AlGaN极化掺杂电流阻挡层的垂直GaN基异质结场效应晶体管结构。在AlGaN极化掺杂电流阻挡层中,通过Al组分渐变而产生的极化电场来提升p型杂质激活率,能更加有效地抑制截止状态下通过极化掺杂电流阻挡层的泄漏电流,从而提升器件的耐压能力。此外,极化掺杂电流阻挡层内空穴浓度的增大会降低器件导通电阻,但由于极化掺杂电流阻挡层与n-GaN缓冲层之间形成的二维电子气会阻挡耗尽层向缓冲层内的扩展,极化掺杂电流阻挡层的使用对器件导通电阻几乎没有影响。     

Transistor failure by secondary breakdown

To solve the problem of transistor failures by transients in inductive load circuits, experiments are performed to monitor the voltage and current waveforms of such transients. It is concluded from this experiment that these failures are caused by secondary breakdown. A model of the local temperature rise is studied and shown to be the possible mechanism of secondary breakdown.     

Modeling of the parasitic transistor-induced drain breakdown inMOSFETs

Parasitic bipolar transistor (PET) induced breakdown characteristics in MOSFETs are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the breakdown voltage for the PET-induced breakdown can be increased by raising the temperature, increasing the channel length, and reducing the substrate resistance     

一种新型结构的光电负阻器件

提出了一种新型结构的硅光电负阻器件———光电双耦合区晶体管(photoelectricdualcoupledareatransistor,PDUCAT) ,它是由一个P+ N结光电二极管和位于两侧的两个纵向NPN管构成的.由于两个NPN管到光电二极管的距离不同,使得它们对光生空穴电流的争抢能力随外加电压的变化产生差异,同时两个NPN管电流放大系数相差较大,最终导致器件负阻现象的出现.文中对PDUCAT进行了工艺模拟和器件模拟,围绕着负阻的形成机理和影响器件性能的主要参数进行了讨论,初步建立了器件模型.     

光电双基区晶体管(PDUBAT)物理模型探讨

本文通过分析器件内部电流传输探讨了光电双基区晶体管(PDUBAT)负阻特性产生机理,首次提出了PDUBAT负阻形成的原因是其输出管横向输出电流的反馈作用,这一看法得到了实验验证.