传输线网络瞬态响应灵敏度分析方法

针对传输线网络瞬态响应灵敏度分析问题,提出了一种采用快速傅里叶变换的灵敏度分析方法。方法从描述整个传输线网络特性的电路方程出发,将传输线网络瞬态响应灵敏度转化为求解传输线网络瞬态响应以及网络参数矩阵对电路参数的偏导数,实现了传输线网络任意节点瞬态响应对任意网络参数的灵敏度分析。该方法无需对耦合传输线进行解耦,能够分析任意类型传输线及任意负载。算例结果表明,方法正确有效。     

用配点法实现传输线瞬态响应的灵敏度分析

给出了一种基于配点法的传输线灵敏度分析方法。首先将传输线方程用切比雪夫多项式的数学模型进行表示,然后进行配点处理获得新形式的矩阵方程,从而方便地求解出传输线的瞬态响应相对于传输线参数和终端负载参数的灵敏度。仿真结果表明该方法有较高的精确度。     

混响室“全向辐照”电磁环境场线耦合规律分析

基于传输线原理,通过构建均匀分布在单位球面的入射电磁波模拟混响室内"全向辐照"电磁环境,建立了混响室散射场条件下场线耦合模型.利用此模型对双线传输线进行数值模拟,研究了传输线的长度、终端负载等关键参数对响应信号的影响.结果表明:传输线对混响室散射场条件下的"全向辐照"电磁环境有明显的选频特性,终端负载响应信号的峰值出现在以线缆长度为波长的频点的n/2倍处,其中n=1,2,3…;传输线终端负载阻值的变化不会对其响应曲线的变化规律产生影响,但会影响其响应峰值;传输线其中一个端口的负载阻值变化不会显著影响另一端负载响应信号.     

谈谈传输线教学的重要性

在现代高速集成电路中,传输线具有分布参数的性质。由于 传输线效应,直接关系到现代高速 VLSI电路的发展。因而促进人们重新认识传输线数学的重要性。     

基于LT spice的传输线波状态分析

通过多个集总电路级联的方式来模拟传输线,利用LTspice的列表功能对不同状态下的模拟传输线进行测试分析,仿真计算其特征阻抗、反射系数、电压驻波比等重要参数,系统的说明了传输线源端阻抗和终端负载阻抗对电磁波状态的影响.     

传输线网络瞬态响应灵敏度分析

在传输线网络瞬态响应灵敏度分析之中,提出了一种基于NILT的新的分析方法。该方法将传输线及其效应连同电子元器件及单元电路作为一个整体,根据传输线在电路中的拓扑关系,将传输线网络瞬态响应灵敏度分析问题转化为求解传输线网络瞬态响应问题,以及传输线ABCD矩阵对电路参数的偏导数问题。通过将ABCD矩阵进行级数展开,极大地简化了ABCD矩阵对电路参数偏导数的计算以及传输线网络瞬态响应灵敏度的分析。本文方法不需要对耦合传输线进行解耦,具有简单、精确、高效等特点,算例结果表明了本文方法的有效性。     

高速高压超短脉冲在容性负载上的测量及分析

高速高压超短脉冲在多个领域具有广泛的应用。利用传输线终端反射的原理和高速开关产生高速高压的超短脉冲信号是一种通用办法。然而，当脉冲信号加载到一个容性负载时，终端负载的不匹配会导致信号的反射。反射信号可能再次回到负载器件上，形成二次导通，并带来应用上缺陷。本文通过理论分析和仿真实验，提出了一些改进措施，可以有效抑制反射信号。     

非零初始状态传输线瞬态分析

本文结合付里叶变换和拉氏变换技术，得出了具有任意非零初始电压、电流分布的多导体传输线的等效时域线性网络模型，传输线可以为有耗丰均匀性，该模型可与常用电路分析软件接口，因而可处理非线性终端负载，给出了一个应用本文模型进行瞬态分析的例子。     

基于路的方法导出耦合微带线的传输方程

在研究传输线时,当传输线的几何尺寸l与工作频率所对应的波长λ可相比拟时,传输线就要用分布参数电路来讨论,在研究分布参数电路时,可以应用电磁场理论,也可以采用电路理论,采用后者,用等效的方法将耦合微带传输线等效为分布参数电路模型,然后用基尔霍夫定律求出其传输线方程。     

基于传输线方程的多根非平行传输线串扰分析

非平行结构的传输线在电力电子系统中普遍存在,当其上通有电压和电流信号时,会在周围传输线上产生串扰响应。采用时域传输线方程建立多根非平行传输线之间的串扰模型,结合FDTD方法,分析在脉冲集总源激励下受扰导线始端和终端负载上的串扰电压响应特性,将其结果与仿真结果对比,验证了该方法的正确性。研究结果表明,非平行结构中受扰线始端和终端负载上的串扰电压响应随着传输线离地面高度的增大而增大,随着传输线之间夹角的增大而变小,且减小的趋势逐渐减弱,从而为线缆间的串扰防护提供了参考依据。     

Realistic statistical worst-case simulations of VLSI circuits

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of VLSI circuits. Gradient analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2 μm 64 K CMOS static RAMs (SRAMs),     

Finite Element Method Applied to Skin-Effect Problems in Strip Transmission Lines

This paper describes a two-dimensional finite element approach to the quasi-static TEM analysis of shielded or open conducting strips with applications to VLSI parasitic elements and transmission line characteristics of printed circuits. The approach uses a combination of two-dimensional and one-dimensional finite elements to solve the field problems in terms of the magnetic vector potential in the frequency domain. The method and the algorithm can be applied to shielded or open conducting strips and takes into account the skin effect and proximity effect between structures. The ac resistance and reactance calculated by rising this approach can be used as input parameters to a circuit analysis program such as SPICE or similar programs.     

高速集成电路芯片内互连线的计算机辅助分析

分析了高速集成电路芯片内互连线的时域特性。首先运用全波方法提取互连线的频变等效电路参数。在此基础上运用数值反拉普拉斯变换 ( NILT)法分析互连电路的时域响应。在分析过程中 ,提出或运用了一些提高精度或效率的技术和方法。分析结果表明 ,该方法很适合高速集成电路芯片内互连线的计算机辅助分析。     

A model for coplanar waveguide transmission line structures onsemiconductor substrates

An accurate model for coplanar waveguide transmission line structures on semiconductive substrates is presented. The model is useful for simulating long (> 0.5 mm) interconnects on LSI and VLSI GaAs circuits as well as high speed Si ICs. When simulated in the frequency domain, the model shows an excellent match to measured S parameters of coplanar waveguide samples     

Accurate estimation of defect-related yield loss in reconfigurableVLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method     

Reliability of majority voting based VLSI fault-tolerant circuits

The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

基于CMOS对数域积分器的小波变换模拟VLSI实现

提出了一种基于CMOS对数域积分器的连续Marr小波变换模拟VLSI实现方法.构造了Marr母小波时域逼近函数模型,用Levenbery-Marquardt非线性最小二乘法求解模型参数最优解,得到母小波逼近函数.设计了以CMOS对数域积分器为积木块的小波变换电路,该电路由冲激响应为母小波逼近函数及其伸缩函数的滤波器组构成,滤波器组采用低灵敏度的IFLF结构进行综合.SPICE仿真结果表明该方法的可行性.     

基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现:脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明:该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield