Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

Impact of laminate cracks under solder pads on the fatigue lives of ball grid array solder joints

This paper reports how the solder joint fatigue lives of three types of lead free plastic BGA components were affected by cracks formed in the printed PCB laminate during a thermal cycling test. The investigation showed that cracks were formed in the laminate for all three tested components. For one of the components having a large chip with solder joints located under the chip, very large cracks were formed in the PCB laminate beneath some solder pads.For lead-free solder joints to BGA components consisting of near eutectic solders based on tin, silver and copper, a large fraction of the solder joints may consist of one single tin grain. Due to anisotropy of tin grains, each solder joint to a BGA component will experience a unique stress condition which will make laminate cracking more likely under certain solder joints.The laminate cracks increased the flexibility of the joints and thereby improved the fatigue lives of the solder joints. Therefore, an estimation of the fatigue lives of solder joints to BGA components based on the results from a thermal cycling test may lead to an overestimation of the fatigue lives if products will be exposed to smaller temperature changes in the field than in the test.If cracks are not formed in the PCB laminate, or if the extent of cracking is small, single-grained solder joints can be expected to result in a high spread in failure distribution with some quite early failures.     

弯曲应力状况下微型BGA封装可靠性比较研究

微型球栅阵列（μBGA）是芯片规模封装（CSP）的一种形式,已发展成为最先进的表面贴装器件之一。在最新的IxBGA类型中使用低共晶锡．铅焊料球,而不是电镀镍金凸点。采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000～1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Q。接近500S·℃时,出现寿命最大值。最佳Qη范围在300-750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热N数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。     

LGA焊点形态对焊点寿命影响的有限元分析

通过Surface Evolver软件对LGA焊点进行了三维形态预测,利用有限元数值模拟对LGA焊点在热循环条件下寿命进行了分析。研究了热循环条件下LGA焊点的应力应变分布规律,随着焊点远离元件的中心位置焊点所受到的等效应力、等效应变和塑性应变能密度逐渐增大,从而得出处于外面拐角的焊点最先发生失效的结论。基于塑性应变范围和Coffin-Manson公式计算了焊点热疲劳寿命;找出了LGA焊点形态对焊点寿命的影响规律,模板厚度一定时PCB焊盘尺寸小于上焊盘时LGA焊点的热疲劳寿命与PCB焊盘尺寸成正比,大于上焊盘时成反比,大约相等时焊点寿命最大。当PCB焊盘和模板开孔尺寸固定时,通过增大模板厚度来增加焊料体积在一定程度上可提高LGA焊点的热疲劳寿命,但是模板厚度增大到一定值时LGA焊点寿命会逐渐降低。     

弯曲应力状况下微型BGA封装可靠性比较

文中采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000με～-1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Qη接近500s·℃时,出现寿命最大值。最佳Qη范围在300s·℃～750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热因数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。     

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.     

Comparative study of micro-BGA reliability under bending stress

The micro-ball grid array (/spl mu/BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by ordinary surface mount technology. In the latest /spl mu/BGA type, eutectic tin-lead solder ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the /spl mu/BGA's PCB, which is soldered by conventional surface mount technology, has been studied in this paper. The bending cycle test (1000 /spl mu//spl epsi/ to -1000 /spl mu//spl epsi/), is used to investigate the fatigue failure of solder joints of /spl mu/BGA, PBGA, and CBGA packages reflowed with different heating factors (Q/sub /spl eta//), defined as the integral of the measured temperature over the dwell time above liquidus (183/spl deg/C). The fatigue lifetime of the /spl mu/BGA assemblies firstly increases and then decreases with increasing heating factor. The greatest lifetime happens while Q/sub /spl eta// is near 500 second-degree. The optimal Q/sub n/ range is between 300 and 750 s/spl deg/C. In this range, the lifetime of the /spl mu/BGA assembly is greater than 4500 cycles if the assemblies are reflowed in nitrogen ambient. SEM micrographs reveal that both /spl mu/ & P-BGA assemblies fail in the solder joint at all heating factors. All fractures are near and parallel to the PCB pad. In the /spl mu/BGA assemblies cracks always initiate at the point of the acute angle where the solder joint joins the PCB pad, and then propagate in the section between the Ni/sub 3/Sn/sub 4/ intermetallic compound (IMC) layer and the bulk solder. In the CBGA assembly reliability test, the failures are in the form of delamination, at the interface between the ceramic base and metallization pad.     

Board level drop test and simulation of leaded and lead-free BGA-PCB assembly

Leaded and lead-free ball grid array (BGA) components were tested in board level drop test defined in the Joint Electron Device Engineering Council (JEDEC) standard under different load levels. Finite element analysis (FEA) models were established using ANSYS. The stress and strain in the solder joint and the average strain energy density (SED) in the solder–pad interface accumulated in one cycle were calculated using ANSYS/LS-DYNA explicit solver. The results of experiment and simulation were employed to re-calculate the constants contained in the Darveaux model to extend its application to the drop test. Then, FEA models with different height and pitch of solder joints were established to obtain the SED to calculate the fatigue life of solder joint under different geometrical conditions through this modified model. The experiment and simulation reveal that the failures mainly occur in the solder–PCB interface in lower load level, the other way round, in a higher load level, the cracks are more possibly formed in solder–package interface; comparing to dropping in horizontal direction with package faces down, the solder joints are much harder to fail when dropping in vertical direction; An optimal height and smaller pitch of solder joints lead to lowest SED and best reliability in the drop test.     

Thermal Cycling Aging Effect on the Reliability and Morphological Evolution of SnAgCu Solder Joints

In solder ball grid array (BGA) technology, solder joint reliability is one of the critical issues in microelectronics manufacturing industries. In this reliability aging study, Sn3.5AgO.7Cu solder joints were subjected to accelerated temperature cycling (ATC) test in TBGA assembly. Fatigue fracture occurred, very close to the solder/intermetallic compound (IMC) interface, at the TBGA component side due to the larger coefficient of thermal expansion (CTE) mismatch compared to the PCB side. During reflow, needle-type and scallop-type morphologies of (Cu,Ni)₆Sn₅ IMCs were formed at the TBGA component and PCB interfaces. In the process of thermal cycling, a layer of (Ni,Cu)₃Sn₄ IMC grew beneath the (Cu,Ni)₆Sn₅ IMC due to the out diffusion of Ni from the under bump metallization (UBM). After extended thermal cycling aging, Ni-Sn-P IMC was found between the (Ni,Cu)₃Sn₄ IMC and the In₃P layer at the printed circuit board (PCB) interface. Grain ripening and spalling of (Cu,Ni)₆Sn₅ IMC grains into the solder joint was also observed in the process of thermal cycling. The spalling phenomena of (Cu,Ni)₆Sn₅ IMCs was caused by interface structure change and cyclic shear stresses and strains incurred during temperature cycling.     

Thermal cycling aging effects on microstructural and mechanicalproperties of a single PBGA solder joint specimen

This paper reports on an experimental study on how thermal cycling aging exposure changes the solder joint microstructure, intermetallic layer thickness and the residual shear strength and fatigue life in a single plastic ball grid array (PBGA) solder joint specimen. The single BGA solder joint specimen was specially designed to evaluate the microstructure and mechanical properties of three different batches of solder joint after subjected to 0, 500, 1000, and 2000 cycles of thermal cycling aging (-40°C to 125°C). It is important to relate the effects of thermal cycling aging on the changes of the microstructural and intermetallic layer thickness to the residual shear strength and fatigue life of solder joints subjected to thermal cycling aging exposure. The results of this study shows that the microstructural and intermetallic development due to thermal cycling aging has a major impact on the residual mechanical and fatigue strength of the solder joint. It was noted that the solder joint shear strength and residual fatigue life degrades with exposure to thermal cycling aging     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

Random vibration reliability of BGA lead-free solder joint

Solder joint fatigue failure under vibration loading has been a great concern in microelectronic industry. High-cycle fatigue failure of lead-free solder joints has not been adequately addressed, especially under random vibration loading. This study aims to understand the lead-free solder joint behavior of BGA packages under different random vibration loadings. At first, non-contact TV Laser holography technology was adopted to conduct experimental modal analysis of the test vehicle (printed circuit board assembly) in order to understand its dynamic characteristics. Then, its first order natural frequency was used as the center frequency and narrow-band random vibration fatigue tests with different kinds of acceleration power spectral density (PSD) amplitudes were respectively carried out. Electrical continuity through each BGA package is monitored during the vibration event in order to detect the failure of package-to-board interconnects. The typical dynamic voltage histories of failed solder joints were obtained simultaneously. Thirdly, failed solder joints were cross-sectioned and metallurgical analysis was applied to investigate the failure mechanisms of BGA lead-free solder joints under random vibration loading. The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases. Solder joint failure locations are changed from the solder bump body of the PCB side to the solder ball neck, finally to the Ni/intermetallic compound (IMC) interface of the package side. The corresponding failure modes are also converted from ductile fracture to brittle fracture with the increase of vibration intensity.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Finite element based fatigue life estimation of the solder joints with effect of intermetallic compound growth

This paper develops an analysis procedure to study the effects of intermetallic compound (IMC) growth on the fatigue life of 63Sn-37Pb (lead-rich)/96.5Sn-3.5Ag (lead-free) solder balls for flip-chip plastic ball grid array packages under thermal cycling test conditions. In this analysis procedure, the thickness of the IMC increased with the number of thermal cycles, and was determined using the growth rate equation. A series of non-linear finite element analyses was conducted to simulate the stress/strain history at the critical locations of the solder balls with various IMC thicknesses in thermal cycling tests. The simulated stress/strain results were then employed in a fatigue life prediction model to determine the relationship between the predicted fatigue life of the solder ball and the IMC thickness. Based on the concept of continuous damage accumulation and incorporated with the linear damage rule, this study defines the damage of each thermal cycle as the reciprocal of the predicted fatigue life of the solder joints with the corresponding IMC thickness. The final fatigue failure of the solder ball was determined as the number of cycles corresponding to the cumulative damage equal to unity. Results show that the solder joint fatigue life decreased as the IMC thickness increased. Moreover, the predicted thermal fatigue life of lead-rich solders based on the effects of IMC growth is apparently smaller than that without considering the IMC growth in the reliability analysis. Results also show that the influence of the IMC thickness on the fatigue life prediction of the lead-free solder joint can be ignored.     

Impact of temperature cycle profile on fatigue life of solder joints

In this paper the influence of the temperature cycle time history profile on the fatigue life of ball grid array (BGA) solder joints is studied. Temperature time history in a Pentium processor laptop computer was measured for a three-month period by means of thermocouples placed inside the computer. In addition, Pentium BGA packages were subjected to industry standard temperature cycles and also to in-situ measured temperature cycle profiles. Inelastic strain accumulation in each solder joint during thermal cycling was measured by high sensitivity Moire interferometry technique. Results indicate that fatigue life of the solder joint is not independent of the temperature cycle profile used. Industry standard temperature cycle profile leads to conservative fatigue life observations by underestimating the actual number of cycles to failure.