Optimum doping profile for minimum ohmic resistance and high-breakdown voltage

The optimum doping profile of a lightly doped layer that introduces the minimum series resistance and sustains a given junction breakdown voltage is derived. The theory applies to a one-dimensional Schottky diode and qualitatively to the collector or drain doping profiles of transistors. The minimum series resistance is found to be about 3.7 × 10^-9Vmin{B}max{2.6}Ω.cm²for an n silicon layer. The optimum doping profile can be closely approximated by a conventional uniformly doped n-n⁺structure.     

Source-to-drain breakdown voltage improvement in ultrathin-film SOIMOSFET's using a gate-overlapped LDD structure

A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n^- region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n^- concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n^- region, which forms the current path, was relaxed effectively at an optimum n^- doping condition     

高压功率集成电路中LDMOS的设计研究

高压功率集成电路(HVPIC),是指将需要承受高电压(达数百伏)的特定功率晶体管和其它低压的控制电路部分兼容,制作在同一块IC芯片上。本文以器件模拟软件MEDICI为工具,用计算机仿真的方法,研究了一种适用于高压功率集成电路的单晶结构的LDMOS的设计问题,其中包括器件的N阱掺杂浓度、衬底浓度、P反型层浓度和结深等主要参数对击穿电压的影响,重点分析了N阱中P型反型层与漏极N^ 区距离Lp对器件耐压的影响,并分析了相应的物理意义。仿真结果表明,Lp对器件耐压有明显的影响。通过优化设计对应于各个参数器件的击穿电压变高,并且受工艺参数波动影响较小,达到了功率集成电路耐压的要求。     

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

The LDD structure, where narrow, self-aligned n^-regions are introduced between the channel and the n⁺source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n^-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n^-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as Vthlowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.     

Unified Breakdown Model of SOI RESURF Device with Uniform/Step/Linear Doping Profile

A unified breakdown model of SOI RESURF device with uniform,step，or linear drift region doping profile is firstly proposed.By the model,the electric field distribution and breakdown voltage are researched in detail for the step numbers from 0 to infinity.The critic electric field as the function of the geometry parameters and doping profile is derived.For the thick film device,linear doping profile can be replaced by a single or two steps doping profile in the drift region due to a considerable uniformly lateral electric field,almost ideal breakdown voltage,and simplified design and fabrication.The availability of the proposed model is verified by the good accordance among the analytical results,numerical simulations,and reported experiments.     

均匀、阶梯和线性掺杂漂移区SOI RESURF器件的统一击穿模型

提出了一个均匀、阶梯和线性掺杂漂移区SOI高压器件的统一击穿模型.基于分区求解二维Poisson方程,得到了不同漂移区杂质分布的横向电场和击穿电压的统一解析表达式.借此模型并对阶梯数从0到无穷时器件结构参数对临界电场和击穿电压的影响进行了深入研究.从理论上揭示了在厚膜SOI器件中用阶梯掺杂取代线性漂移区,不但可以保持较高的耐压,而且降低了设计和工艺难度.解析结果、MEDICI仿真结果和实验结果符合良好.     

Design criteria for GaAs MESFETs related to stationary high field domains

Using a modified theory of the high-field domains which takes into account the field-dependent diffusion we show that the existence of the high-field domain at drain side of the gate in GaAs MESFETs leads to a new set of design criteria which should be met to achieve the optimum performance. We derive these criteria and estimate the drain-to-source breakdown voltage and the maximum power of the device as functions of the doping density and device dimension. We also estimate the optimum gate length, the thickness of the active layer, the drain-to-gate separation and the doping level as functions of frequency. It is demonstrated that a larger than conventional drain-to-gate separation might be necessary for power devices to house a fully developed highfield domain and to avoid a premature breakdown at the drain. Our estimates indicate that the maximum power at 10 GHz can reach a theoretical limit of about 20 watts for class A operation.     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.     

A self-limiting anodic etch-to-voltage (AETV) technique for fabrication of modified read-impatts

The use of modified Read doping profiles in IMPATT diodes has resulted in a dramatic increase in microwave efficiency compared to the standard IMPATT with a constant doping profile. However, the modified Read-IMPATT profile demands a more stringent material control than does the uniform profile to achieve a specific-frequency device. A self-limiting anodization technique is described which is ideally suited for the fabrication of controlled breakdown voltage (i.e. controlled frequency) modified Read-IMPATTs. For any doping profile where the breakdown voltage increases as the anodization proceeds, the process can be made self-limiting by setting the anodization voltage at the desired breakdown voltage.Experimental data are presented which show much improved control in achieving both a specific breakdown voltage device and minimizing the effect of lateral doping profile variations. Data on Read-IMPATTs diodes made from anodized material demonstrate the expected high efficiency microwave performance and are as resistant to microwave tuning induced burnouts as Read-IMPATT diodes made without anodization.The effect of epi-loss mechanisms arising from the interaction of Pt with GaAs during the formation of the device Pt Schottky barrier and/or the thinning by anodization of GaAs in aqueous solutions under zero applied voltage conditions is discussed. Once recognized, allowance can be made in the AETV processing for the voltage shift resulting from these epi-loss mechanisms to minimize these second order effects.     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

薄外延阶梯掺杂漂移区RESURF耐压模型

提出薄外延阶梯掺杂漂移区RESURF结构的耐压解析模型。借助求解二维Po isson方程,获得薄外延阶梯掺杂漂移区的二维表面电场和击穿电压的解析表达式。基于此耐压模型研究了不同阶梯漂移区数(n=1、2、3、5)的击穿特性,计算了击穿电压与结构参数的关系,其解析结果与数值结果吻合较好。在相同长度下,阶梯掺杂漂移区结构(n=3)击穿电压由均匀漂移区(n=1)的200 V提高到250 V,增加25%。该模型可用于薄外延阶梯掺杂和线性掺杂漂移区RESURF器件的设计优化。     

Optimum design and fabrication of InAlAs/InGaAs HEMT's on GaAs withboth high breakdown voltage and high maximum frequency of oscillation

A simple model to describe the dependence of the breakdown voltage between gate and drain on width of the gate recess in an InAlAs/InGaAs high electron mobility transistor (HEMT) is presented. In this model, the depletion region laterally spreads to the drain region. It enables us to express the dependence of device parameters on the width of the gate recess. The model suggests that the breakdown voltage increases with the width of the gate recess and then saturates, which is experimentally confirmed. Calculations based on the model show that the maximum frequency of oscillation (f_max) also increases with the width of the gate-recess due to the reduction in both the drain conductance and the gate-to-drain capacitance, and then slightly decreases with the width due to the increase in the source resistance. We fabricated InAlAs/InGaAs HEMT's lattice-mismatched on GaAs substrates with optimum recess-width, and these exhibited both a high breakdown voltage of 14 V and a high f_max of 127 GHz at a gate length of 0.66 μm     

A novel high performance stacked LDD RF LDMOSFET

A novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using a simple yet effective concept of stacked lightly doped drain (LDD), is proposed. The stacked layers of LDD minimizes the on-state resistance of the transistor due to the n+ doping used in the top LDD layer, and also raises the device breakdown voltage due to the charge compensation in the composite LDD region. Therefore, for the same blocking voltage rating, the stacked LDD structure allows the LDMOSFET to have a higher current handling capability. This in turn causes the transconductance Gm to be higher, leading to higher RF performance for the power device. Measured results show that a 67% improvement in I_dsat and a 16% improvement in forward blocking voltage are obtained. Furthermore, the new device achieves an increase in transconductance of 145% and improves cut-off frequency by 108% at a gate voltage of 10 V     

变漂移区厚度SOI横向高压器件的优化设计

提出了一种耐压技术——横向变厚度VLT技术,以及基于此技术的一种高压器件结构——变厚度漂移区SOI横向高压器件,借助二维器件仿真器MEDICI,深入研究了该结构的耐压机理。结果表明,变厚度漂移区结构不但可以使横向击穿电压提高20%,纵向击穿电压提高10%,而且可以使漂移区掺杂浓度提高150%～200%,从而降低漂移区电阻,使器件优值提高40%以上。进一步研究表明,对于所研究的结构,采用一阶或二阶阶梯作为线性漂移区的近似,可以降低制造成本,并且不会导致器件性能的下降。     

Short-channel MOS transistors in the avalanche-multiplication regime

Short-channel MOS transistors have been analyzed in the avalanche-multiplication regime. Ionization integrals, internal body effect, and parasitic bipolar turn-on have been investigated in dependence of channel doping profile and substrate doping level. Results of a two-dimensional numerical analysis offer a better understanding of the breakdown mechanisms. For devices with shallow channel doping and high-resistivity substrate, an avalanche-current-induced barrier lowering at the source junction edge is observed. Electron injection via this locally lowered barrier triggers parasitic bipolar action. A deep channel implant improves the source barrier and lower substrate resistivity shifts the parasitic bipolar trigger voltage to higher drain voltage (1-1.5 V).     

Increase of critical current density and voltage for triggering avalanche injection through use of graded collector doping

In this paper it is shown that both critical current density and voltage of an epitaxial bipolar power transistor with an inductive load, which are taken as a measure of its susceptibility to avalanche injection, can be significantly increased by using double graded collector doping profiles. The first graded portion gives the required current protection level and the steeper second graded profile can be used to increase the voltage protection level. Calculations are carried out for optimum collector parameters to achieve minimum resistance for the required open base breakdown voltage. Results are compared with uniformly doped profile for the same collector resistance and open base voltage. It is shown that a device with graded collector is less prone to failure due to avalanche injection.     

A 600-volt MOSFET designed for low on-resistance

A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.     

Optimization of nonplanar power MOS transistors

Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm²active area. With a high channel width packing density design and 2.5-mm²active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratioR_{off}/R_{on}of approximately 10¹⁰for a 20-V variation in gate-to-source voltage.