A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-/spl mu/m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm/sup 2/ die area including the ESD I/O pads.     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

A SiGe BiCMOS 24-GHz receiver front-end for automotive short-range radar

This paper presents a fully integrated SiGe BiCMOS 24-GHz receiver front-end implemented for a ultra-wideband automotive short-range radar sensor. The circuit consists of a homodyne I/Q down-converter and a 24-GHz synthesizer. The receiver front-end is able to achieve a power conversion gain as high as 30 dB and a 6-dB noise figure, while preserving high linearity performance thanks to a 1-bit gain control. The frequency synthesizer, which also includes an on-chip loop filter, guarantees a phase noise of −104 dBc/Hz at 1-MHz offset from the 24.125-GHz carrier and a 4.7-GHz tuning range from 20.4 to 25.1 GHz.     

一种用于双波段GPS接收机的低功耗宽带CMOS频率合成器

提出了一种用于双波段GPS接收机的宽带CMOS频率合成器.该GPS接收机芯片已经在标准O.18μm射频CMOS工艺线上流片成功,并通过整体功能测试.其中压控振荡器可调振荡频率的覆盖范围设计为2～3.6GHz,覆盖了L1,L2波段的两倍频的频率点.并留有足够的裕量以确保在工艺角和温度变化较大时能覆盖所需频率.芯片测试结果显示,该频率综合器在L1波段正常工作时的功耗仅为5.6mW,此时的带内相位噪声小于-82dBc/Hz,带外相位噪声在距离3.142G载波1M频偏处约为-112dBc/Hz,这些指标很好地满足了GPS接收芯片的性能要求.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

Fully integrated W-CDMA IF receiver and IF transmitter including IFsynthesizer and on-chip VCO for UMTS mobiles

A fully integrated, dual intermediate frequency (IF) receiver and an IF transmitter, each with on-chip IF synthesizer, for use in third-generation wide-band code division multiple access (W-CDMA) mobiles has been implemented in a standard, high-frequency, Si-bipolar process with an f_T of 25 GHz. The IF receiver (318 MHz) and IF transmitter (285 MHz) include a complete phase-locked loop (PLL) and on-chip voltage-controlled oscillator (VCO) with integrated varactors and transformers. The VCOs are used for on-chip local oscillator (LO) generation and operate at four times IF, 1272 MHz and 1140 MHz, for Rx and Tx, respectively. Fully integrated, active, analog base-band filters further increase functionality and integration level. In the receiver, a channel select filter, composed of a fifth-order Chebyshev lowpass filter and a first-order all-pass filter, is implemented. In the transmitter, a fifth-order Butterworth low-pass filter functions as a reconstruction filter. Both devices operate on 2.7-3.3-V supply. The designs comply with ARIB W-CDMA and UMTS standards. Each chip is mounted in a small outline, 32-pin, leadless surface mount package     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

A CMOS broadband frequency synthesizer for DVB-C receiver

A 70∼900 MHz broadband PLL frequency synthesizer is developed for the single conversion DVB-C receiver in a standard 0.25 μm CMOS technology. The true 3-band VCO with a novel AAC (Auto-Amplitude Control) circuit provides a wideband amplitude stable output and a reliable startup without degrading the phase noise performance. A 16/17 dual-modulus prescaler with a new logic structure has increased the speed. The charge pump current is programmable for wide loop stabilization and phase noise optimization. The measured results show that the locked range of the frequency synthesizer is 70∼900 MHz. The worst phase noise at 1 k/10 k/100 k/1 MHz offset frequency is ordinal −65/−85/−112/−128 dBc/Hz and the spur at reference frequency is lower than −90 dBc.The frequency synthesizer chip dissipates only 16.2 mA from a 3.3 V supply.     

A high sensitivity and wide dynamic range zero-IF RF receiver for cognitive radio application

This paper presents an RF receiver of zero-Intermediate Frequency (IF) architecture for Cognitive Radio (CR) communication systems. Zero-IF architecture reduce the image reject filter and IF filter, so it is excellent in low cost, compact volume, and low power dissipation. The receiver employs three digital attenuator and a high gain, high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of −81 dBm. A fully balanced I/Q demodulator and a differential Local Oscillator (LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage. In order to select an 8 MHz-channel from 14 continuous ones located in UHF band (694–806 MHz) accurately, approach of channel selectivity circuits is proposed. The RF receiver has been designed, fabricated, and test. The measured result shows that the noise figure is 3.4 dB, and the error vector magnitude is 7.5% when the input power is −81 dBm.     

A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider

A fully integrated Sigma-delta fractional-N frequency synthesizer is realized in TSMC 0.18 μm MM/RF 1P6M Salicide 1.8V/3.3V technology. The proposed implicit dual-path loop filter with enhanced trans-conductor can eliminate the charge pump mismatch of the conventional dual-path loop filter and suppress the effect of parasitic poles and zero as well as reduce the area of the loop filter. A simple frequency divider based on phase switching technique is employed to reduce the area and power dissipation. The frequency synthesizer consumes 21 MW power from 1.8 V power supply voltage with area 1.80  ×  2.0 mm². The achieved phase noise is −82 dBc/Hz at 10 kHz offset, −108 dBc/Hz at 100 kHz offset and −128 dBc/Hz at 1 MHz offset respectively with frequency switching time 95 μs.     

A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC

This work presents a shared fractional-N synthesizer used by two dual-band 802.11 radios integrated on a single chip for 2/spl times/2 multiple-input multiple-output (MIMO) applications. Additional 2/spl times/2 MIMO chips can be used in a system by phase synchronizing the signal paths through a bidirectional LO porting scheme developed for this application. This synthesizer was fully integrated with the exception of an off-chip loop filter. The synthesizer is a /spl Delta//spl Sigma/-based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in the IEEE 802.11a/b/g and Japanese WLAN standards. The radio uses a variable IF frequency so that both the RF LO and IF LO can be derived from a single synthesizer saving chip area and power. The synthesizer includes a programmable second/third-order /spl Delta//spl Sigma/ noise shaper, a phase frequency detector, a differential charge pump, and a 6-bit multimodulus divider (MMD). The nominal jitter from 100 Hz to 10 MHz is 0.63-0.86/spl deg/ rms in the 5-GHz band and 0.35-0.43/spl deg/ rms in the 2.4-GHz band. The maximum frequency deviation of the synthesizer when enabling the transmitter is less than 150 kHz and the frequency error settles to 2 kHz in less than 12 /spl mu/s. For MIMO applications requiring more than two full paths, a single synthesizer on one die can be used to generate the LOs for all other radios integrated in different dies.     

80 MHz bandpass delta-sigma modulator using switched-capacitorresonator structure

A fully differential 80 MHz fourth-order bandpass ΔΣ modulator, meant for a 100 MHz GSM/WCDMA multimode IF receiver, is presented. The modulator is based on a double-delay single opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the centre frequency of the topology is insensitive to different component variances. The measured peak SNR is 78 dB and 43.3 dB for 270 kHz (GSM) and 3.84 MHz (WCDMA) bandwidths, respectively     

A BJT translinear loop based optoelectronic integrated circuit with variable transimpedance for optical storage systems

A 0.35 μm SiGe BiCMOS optical receiver with voltage-controlled transimpedance is presented. A variable-gain current amplifier using a BJT translinear loop is applied. A transimpedance dynamic range of 1554 (63.8 dB) with the largest transimpedance of 2.84 MΩ, a bandwidth up to 379 MHz, and a transimpedance bandwidth product up to 168 TΩHz are achieved.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

A broadband CMOS intermediate frequency (IF) variable-gain amplifier (VGA) for DRM/DAB tuners is presented. The VGA comprises two cascaded stages: one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18/zm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is-3.9 dBm.     

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.     

A single-PLL dual-PPF synthesizer for Mode-1 MB-OFDM UWB communication

A frequency synthesizer incorporating a single-PLL and single-sideband (SSB) mixers for Multi-Band OFDM Mode-1 UWB application is presented in this paper. The proposed synthesizer employs RC poly phase filter to suppress unwanted tones and correct phase and amplitude errors between quadrature paths. Fabricated in a 0.18-μm CMOS technology, this circuit achieves a sideband rejection of −32.27 dB, integrated phase noise of 2.138°, and a switching time of less than 2.05 ns while consuming 66 mW from a 1.8-V supply.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.