VLSI版图验证系统中参提取方法的研究

本文研究了ＶＬＳＩ版图验证系统中电阻及电容提取的方法，总结了各种方法的优缺点，并给出了当前参数提取方面的研究向和发展趋势。     

在Transputer并行加速器上实现并行的版图参数提取

本文叙述了ＶＬＳＩ ＣＡＤ中版图参数提取并行算法在Ｔｒａｎｓｐｕｔｅｒ并行加速器上的实现。参数提取的并行算法是利用图形运算的区域并行性将版图划分为与处理器数目相等的若干区域，然后并行地在各处理器中完成对应区域的版图参数提取。用保持划分区域内图形向量数相等的方法，使各处理器负载均衡，经计算证实，各处理器负载均衡性较好，大大提高了运行速度。Ｔｒａｎｓｐｕｔｅｒ并行加速器具有优良的性能价格比，在其上实现     

3-D寄生电阻电容线性元计算的并行实现

ＶＬＳＩ电路中，深亚微米工艺及多层布线技术的广泛应用使互连寄生效应成为制约电路性能的主要因素，直接边界元素法３－Ｄ寄生电阻电容提取的计算量很大，采用并行计算是快速提取的重要途径之一。     

3—D寄生电阻电容线性元计算的并行实现

ＶＬＳＩ电路中，深亚微米工艺及多层布线技术的广泛应用使互连寄生效应成为制约电路性能的主要因素，直接边界元素法３－Ｄ寄生电阻电容提取的计算量很大，采用并行计算是快速提取的重要途径之一。     

用边界元法提取VLSI版图电阻

介绍了ＶＬＳＩ版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。该算法采用变节点单元，较好地解决了实际问题中经常出现的角点问题。通过应用该算法对几个实例进行提取，证明使用本文的算法不仅在精度上而且在占用ＣＰＵ时间上都取得了令人满意的效果     

VLSI版图参数提取的分布式并行算法

在用边界元法提取版图参数时,经常会遇到非均匀介质的情况。对这类问题若直接用传统的边界元分区方法求解,处理起来比较麻烦,尤其当非均匀性较严重时,边界元法计算简单方便、速度快的优点会大大削弱。针对这一现象。本文提出了边界元分区问题的分布式并行算法。将它用于一个由天台工作站组成的分布式环境中对ＶＬＳＩ版图参数进行提取,运行时间比传统方法明显减少,证明该算法加快了求解的速度,具有并行、高效的特点,取得了良     

开关电容—∑△调制器设计中电容值的计算

采用开关电容技术设计∑△调制器适应了ＶＬＳＩ的发展本文提出了一种利用系数匹配原理,确定开关电容网络元件值,;实现传输函数的方法。     

基于线扫描的VLSI版图几何验核心算法的固化

ＶＬＳＩ集成度的飞速提高使设计过程复杂化，也对版图验试工具的处理能力与能力提出了更高的要求。将版图验证的核心算法固化在专用硬件上，是一类非常有效的方法。     

性能驱动系统划分的均场退火方法

本文通过把时延约束条件转化为一个布尔矩阵，利用这个布尔矩阵构造能量函数的时延约束项，从而解决了用神经网络处理时延约束这类不等式约束的难题，并据此提出了一个性能驱动的ＶＬＳＩ系统划分的均场退火算法．算法不仅考虑了模块间的连接关系，还考虑了版图的物理结构，是一种逻辑与版图相结合的划分方法．实验表明，该算法具有较强的寻优能力     

硬件描述语言VHDL及其应用

ＶＨＤＬ是一种超高速ＶＬＳＩ硬件描述语言，能对集成电路的功能和结构进行描述，用ＣＡＤ软件将其编译和转换，并自动形成线路，概要地介绍了ＶＨＤＬ的设计组织和数据类型，并对ＶＨＤＬ的特点及其在ＶＬＳＩ设计中的应用要点做了一些探讨。     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

An efficient solver for the three-dimensional capacitance of theinterconnects in high speed digital circuit by the multiresolutionmethod of moments

The computation of the equivalent capacitances for three-dimensional (3-D) interconnects features large memory usage and long computing time. In this paper, a matrix sparsification approach based on multiresolution representation is applied with the method of moments (MoM) to calculate 3-D capacitances of interconnects in a layered media. Instead of direct expansion of the charge distribution by the orthogonal wavelet basis functions, the large full matrix resulting from discretization of the integral equations is taken as a discrete image and sparsified by two-dimensional (2-D) multiresolution representations. The inverse of the obtained sparse matrix is efficiently implemented by Schultz's iterative approach. Several numerical examples are given and the results obtained show that the proposed method significantly sparsifies the matrix equation and the capacitance parameters computed by the matrix equation with high sparsity agree well with the results of other reports and those computed by an established capacitance extractor FASTCAP     

区域分裂法在提取多层介质中多导体三维复杂互连结构电磁参数中的应用

本文首次将区域分裂法（ＤＤＭ）用于多层介质中多导体三维复杂互连结构的电磁参数的提取，可以快速、准确地提取复杂互连结构的静态电容矩阵。由于区域分裂法能肥大问题化为若干独立的小问题，不仅可以缩小计算规划，而且可以在该算法框架下灵活地组合各种三维互连结构，具有很强的灵活性，再充分利用集成电路结构分层的特点，对各个小问题采用最恰当的计算方法，从而可大大减少整体设计所需的时间和存储空间。文中给出的计算结果Ａ     

Capacitance computations in a multilayered dielectric medium usingclosed-form spatial Green's functions

An efficient method to compute the 2-D and 3-D capacitance matrices of multiconductor interconnects in a multilayered dielectric medium is presented. The method is based on an integral equation approach and assumes the quasi-static condition. It is applicable to conductors of arbitrary polygonal shape embedded in a multilayered dielectric medium with possible ground planes on the top or bottom of the dielectric layers. The computation time required to evaluate the space-domain Green's function for the multilayered medium, which involves an infinite summation, has been greatly reduced by obtaining a closed-form expression, which is derived by approximating the Green's function using a finite number of images in the spectral domain. Then the corresponding space-domain Green's functions are obtained using the proper closed-form integrations. In both 2-D and 3-D cases, the unknown surface charge density is represented by pulse basis functions, and the delta testing function (point matching) is used to solve the integral equation. The elements of the resulting matrix are computed using the closed-form formulation, avoiding any numerical integration. The presented method is compared with other published results and showed good agreement. Finally, the equivalent microstrip crossover capacitance is computed to illustrate the use of a combination of 2-D and 3-D Green's functions     

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance     

小波多分辨率分析改进互连结构电容提取

本文将点匹配矢量法矩阵视作类似离散图像信号的一组数字信号矢量,进行小波多分辨率分解对该矩阵进行拟对角化压缩,克服了以往小小基直接展开的矩量法在求解二维与三维电在问题时的困难。文章例子的计算结果说明了这种方法在将矩量法得到的满矩阵变换为稀疏矩阵时具有的效率。电容参数提取的效率也由于矩阵的稀疏化得到了提高。文中的数据值结果与文献及ＦＡＳＴＣＡＰ软件的结果吻合。     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

Surface Current Modelling of the Skin Effect for On-Chip Interconnections

In this paper, the skin effect for 2-D on-chip interconnections is predicted using a recently developed differential surface admittance concept. First, the features of the new approach are briefly recapitulated and details are given for a conductor with rectangular cross-section. Next, the 1-D situation is studied as a limiting case of the 2-D situation. The relationship with a local impedance formulation is investigated and illustrated with a numerical example. Finally, the new method is used to determine inductance and resistance matrices of 2-D on-chip interconnect examples with specifications taken from the international technology roadmap for semiconductors. Extra capacitance data are also provided.     

Theory of ballistic nanotransistors

Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.     

RTD/2-D MESFET logic element for compact, ultra-low-powerelectronics

We describe compact and highly functional logic elements utilizing a two-dimensional (2-D) MESFET with a resonant tunneling diode load. The 2-D MESFET uses two lateral Schottky gate contacts to modulate the width of the 2-D electron gas layer. The novel contact geometry results in reduced gate capacitance, ultra-low-power performance, and the elimination of the Narrow Channel Effect (NCE) compared to conventional HFETs or MESFETs. The advantage of using an RTD as the load device is the reduction of the static power consumption at the logical high input level. We demonstrate low-power RTD/2-D MESFET inverter operation as well as compact NAND and NOR gates using a single RTD/2-D MESFET pair. We also present optimized inverter elements and estimate from SPICE simulations the power-delay products of RTD/2-D MESFET ring oscillators. Compared to recently reported values for CMOS on SOI, the RTD/2-D MESFET technology is expected to exhibit one order of magnitude less active power dissipation and a factor of 3 lower power-delay product