AG‐DPA: Assignment game–based dynamic power allocation in multibeam satellite systems

Dynamic power allocation is the key technology to maintain the link quality and improve the system throughput in multibeam satellite systems. Many numerical optimization algorithms have been proposed to optimize the power allocation schemes among beams. However, current metaheuristic algorithms, most of which are off‐line iterative methods, are not appropriate in nonuniform traffic demands and time‐varying channels due to the high computational complexity. To solve this problem, an assignment game–based dynamic power allocation (AG‐DPA) is proposed to achieve the suboptimality with low complexity in multibeam satellite systems. The key idea of the proposed AG‐DPA is to model the DPA problem into an assignment game model where the competitive equilibrium is achieved. Further, an adaptive price factor is introduced to make a trade‐off between algorithm performance and complexity. Simulation results show the effectiveness of the proposed AG‐DPA algorithm.     

一种新型的抗DPA攻击可配置逻辑结构

DPA(Differential Power Analysis)攻击的强度取决于芯片电路功耗与所处理的数据之间的相关性以及攻击者对算法电路实现细节的了解程度.本文结合动态差分逻辑和可配置逻辑的特点,提出了一种具有抗DPA攻击能力的双端输出可配置逻辑(DRCL:Dual-Rail Configurable Logic)....     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

改进型宽带Doherty功率放大器的设计

根据Doherty技术,设计了一款改进型宽频带功率放大器。在设计过程中,分析了λ/4线对Doherty功率放大器(DPA)的影响。通过对阻抗比的研究,在理论上延拓了功放的带宽。此外,应用不对称功率输入结构来克服阻抗比变化所带来的非理想调制效应。为了证明文中的理论分析,采用飞思卡尔公司的LDMOSFET功放管MRF6S20010,最终设计实现了一款工作于1 900～2 200MHz的宽频带Doherty功率放大器。测试结果显示,改进型宽带功放相对于传统Doherty功率放大器有很大的优势,可用于无线通信领域。     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

A broadband Doherty power amplifier with harmonic suppression

In this paper, the design and implementation of the broadband, Doherty power amplifier (DPA) with 2nd and 3rd harmonics suppression, with theoretical analysis is presented. In the proposed structure a novel harmonic suppressed Wilkinson power divider used in DPA, which results in harmonic suppression with high level of attenuation. Moreover the proposed DPA has major advantages in terms of the linearity and works on a wideband frequency range (2.1–2.7 GHz) with minimum 40% drain efficiency (DE). The linearity of the proposed DPA is increased extremely, which significant improvement (7 dBm) is achieved from the main amplifier. In the proposed DPA, the main and the auxiliary amplifiers are implemented using Class-AB and Class-C topology respectively with equal MRF6S27015N MOTOROLA transistors in LDMOS technology.     

对智能卡进行微分功耗分析攻击的方法研究

详细阐述了对通用密码系统实施微分功耗分析攻击(DPA)的理论基础和对DES算法攻击的特定理论，并提出了对DPA的改进算法。在分析功耗信号的噪声特点以后，提出了一个信噪比(SNR)的建模方法和相应理论的证明。最后，给出了算法的一个实验结果。     

Adiabatic differential voltage switch logic

To diminish the trapped charges in internal nodes of the complex logic adiabatic gate, adiabatic differential voltage switch logic (ADVSL) using capacitance coupling technique is presented. An adiabatic system, based on a relatively small number of complex ADVSL gates, reduces not only dissipation loss, but also the gate count greatly.     

A Distributed Power Allocation Scheme for Base Stations Powered by Retailers with Heterogeneous Renewable Energy Sources

Owing to the intermittent power generation of renewable energy sources (RESs), future wireless cellular networks are required to reliably aggregate power from retailers. In this paper, we propose a distributed power allocation (DPA) scheme for base stations (BSs) powered by retailers with heterogeneous RESs in order to deal with the unreliable power supply (UPS) problem. The goal of the proposed DPA scheme is to maximize our well‐defined utility, which consists of power satisfaction and unit power costs including added costs as a non‐subscriber, based on linear and quadratic cost models. To determine the optimal amount of DPA, we apply dual decomposition, which separates the master problem into sub‐problems. Optimal power allocation from each retailer can be obtained by iteratively coordinating between the BSs and retailers. Finally, through a mathematical analysis, we show that the proposed DPA can overcome the UPS for BSs powered from heterogeneous RESs.     

DES芯片抵御高阶差分功耗分析攻击方法研究

分析独特的屏蔽方法及改进方法的不足,提出了逻辑层和算法层相结合抵御高阶差分功耗分析攻击的新方法,并给出芯片半定制设计流程.芯片关键部分电路采用自定义功耗恒定逻辑单元实现,非关键部分电路采用CMOS逻辑以减少功耗和面积.整体电路采用独特的屏蔽方法自定义轮实现.结果表明芯片能够抵御高阶差分功耗分析攻击,运算速度与现有方法相当,而所需资源比现有方法少.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

线性Doherty功放的优化设计

设计了一个高效率、高线性度的射频Doherty GSM基站功放。利用Doherty功放的载波放大器与峰值放大器之间的互调对消技术使Doherty功放的三阶互调干扰(IMD3)改善了11dBc;并通过相位补偿延迟线的前置处理进一步提高了功放的效率,使其效率比常用的平衡补偿线方案提高了4%左右。文中利用两个MRF9060功放管制作了一个GSM频段Doherty功放,其实测1dB压缩点功率(P1dB)达到了130W;双音测试表明:经过4.5dB的回退后三阶互调失真(IMD3)优于-35dBc,此时功率附加效率(PAE)高达47.3%;WCDMA 3GPP的测试结果表明:经过6dB回退后,其5MHz偏移量的邻道功率比(ACPR)优于-40.5dBc,PAE为43.5%,比AB类平衡功放的效率提高了17.8%。结果表明:该设计方案较好地解决了射频功放功率与效率之间的矛盾,适用于射频功放的设计。     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

Fuzzy logic–based distributed clustering protocol to improve energy efficiency and stability of wireless smart sensor networks for farmland monitoring systems

Wireless smart sensor networks (WSSNs) are emerging as the physical backbone of the internet of things (IoT) technology. On the basis of the IoT platform, web‐based systems and services are been developing such as e‐surveillance, industrial‐IoT, and precision agriculture. For farmland monitoring systems, WSSNs need to be scalable in terms of coverage area. Sensor nodes are energy‐constrained devices, and hence, many energy‐efficient clustering protocols are developed in the literature. But these methods overload the cluster leaders (CLs) with cluster computation and data communication costs. An improper CL selection may lead to the early death of such nodes and hence does not prolong the network lifetime stability. We propose a fuzzy logic (FL)–based distributed clustering protocol to enhance the energy efficiency of WSSN while maximizing the coverage area. The load of CLs is shared by originators and super‐CLs (SCLs) selected in the network. The wireless link and received signal strength (RSS) are greatly affected by environmental conditions and thus cannot be considered as ideal network parameters. We use FL systems to tackle the uncertainty of such network parameters. The proposed protocol is simulated for different scalable WSSNs. The results indicate that the proposed protocol provides better lifetime stability than the recent conventional protocols. The functionalities of the protocol are proposed considering the recent wireless standards. Hence, the proposed protocol can be suitably implemented for farmland monitoring systems.     

A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor

The existing Power Analysis Attacks (PAA) resilient adiabatic logic designs exhibit variations in current peaks, have asymmetric structures and suffer from Non-Adiabatic Losses (NAL) during the evaluation phase of the power-clock. However, asymmetric structure and variations in current peaks make the circuit susceptible to PAA. In this paper, we present a novel PAA resilient adiabatic logic which has a symmetric structure, completely removes NAL from the evaluation phase of the power-clock and exhibits minimal variations in current peaks for gates as well as in an 8-bit Montgomery multiplier. The proposed logic has been compared with three existing secure adiabatic logic designs for operating frequencies ranging from 1 MHz to 100 MHz and power-clock scaling ranging from 1.8 V to 0.6 V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) at the frequencies mentioned above. In addition, all the 2-input gates using proposed logic dissipate average energy within 0.3% of each other and thus, lowest value of standard deviation at all the simulated frequencies. The simulation results for the 8-bit Montgomery multiplier show that proposed logic exhibits the least value of NED and NSD at all the simulated frequencies and under power-supply scaling.     

智能卡差分能量分析实验平台实现与数据优化

随着密码学和密码芯片的广泛应用,针对密码芯片的攻击也日益增多.差分能量分析（Differential Power Analysis,DPA）攻击是最常见的一种侧信道攻击方法.DPA攻击者无须了解加密算法的具体细节,而只通过密码设备的能量迹分析即可破解出设备的密钥.因此,研究DPA攻击十分必要.实现了智能卡DPA实验系统,并对于此系统的能量迹测量数据进行优化处理,从而更有利于针对此类攻击的分析和相应防御措施的设计.     

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.