An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A CCD wave filter with low sensitivity

Starting with a double terminated Chebyshev LC ladder filter, a CCD wave filter has been implemented by using CCD resonators and charge amplifiers as basic building blocks. The bandpass filter which was realized on a test chip has a center frequency of 50 kHz, together with a relative Chebyshev bandwidth of 2.6 percent, 5 dB insertion loss, and more than 60 dB stopband attenuation. Compared to known SC filters, the advantages of the new approach are in extremely low sensitivity of the center frequency which is controlled by an external clock frequency, and a relative bandwidth which does not depend on the center frequency, but is controlled by capacitance ratios. Filter design, some aspects related to implementation, and experimental results are described.     

A MOS switched-capacitor ladder filter in SIMOX technology for hightemperature applications up to 300°C

This paper describes techniques and methods used to realize a seventh order switched-capacitor low pass filter in SIMOX technology. The filter has Bessel characteristic and a 3 dB-bandwidth of 20 Hz at a clock frequency of 100 kHz. Special design of transistors and transmission gates results in drastically reduced leakage currents at high temperatures. The power supply voltage of the switched-capacitor filter is 10 V. The temperature range is extended up to 300°C. Experimental results of the transistors, the transmission gates, the operational amplifier, and the complete filter are presented     

Design of a high-order single-loop ∑△ ADC followed by a decimator in 0.18 μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma-delta analog-to-digital con verter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm~2.     

Frequency-bandwidth-tunable powerline notch filter for biopotential acquisition systems

Presented is a novel powerline notch filter embeddable into a chopperstabilised instrumentation amplifier for biopotential measurements. The frequency-translation property of the chopper enables the powerline notching to be indirectly implemented by two resonant zeros around the chopper frequency, resulting in substantial silicon area savings. Transistor-level implementation in 90 nm CMOS using a pseudo-LC circuit topology with Q-enhancement demonstrates 50 to 60 Hz frequency tunability, 25/41 dB powerline rejection at 5/30 Hz bandwidth, and 1000x relaxation of time constant under a 4 kHz chopper frequency.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ΣΔ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0–4kHz passband. The 2-tap FIR filter provides more than −53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than −76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0–4kHz bandwidth. The active die area of the fully differential filter is 0.17mm² in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown. Supported by Foundation for University Key Teacher by the Ministry of Education of China     

A 16-bit 250-kHz delta-sigma modulator and decimation filter

This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-μm CMOS technology. It achieves a dynamic range of 94 db     

A low-voltage low-power current-mode high-pass leapfrog filter

A low-power bipolar continuous-time low-frequency high-pass second-order Butterworth filter is presented that works in the current domain and operates from a single 1.3-V battery. The filter contains two adjustable integrators. These integrators are realized by means of a capacitance and an adjustable transconductance amplifier with an indirect output. The complete filter, including all capacitances needed, can be integrated in an ordinary full-custom IC process. A semicustom realization is shown. The filter demonstrates operation down to 1 V with less than 16µW power consumption and a dynamic range of 50 dB. Its cutoff frequency can be exponentially tuned with a control current over a range from 100 Hz to 1 kHz.     

A bipolar voltage-controlled tunable filter

A complete monolithic state variable filter is described which has been fabricated with bipolar technology. Two-quadrant multipliers are used in a novel fashion to achieve integration time constant large enough for audio purposes. Voltage control of frequency response from 20 Hz to above 20 kHz has been achieved without sacrifice of accuracy (notch depth >50 dB, low-pass and bandpass responses accurate to better than 0.1 dB), dynamic range (>90 dB), power supply rejection (PSRR>40 dB) or frequency drift (<200 ppm//spl deg/C). The design has been shown to be generally useful in the design of self-contained bipolar filters.     

An elliptic continuous-time CMOS filter with on-chip automatic tuning

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.     

Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding

The results of the development of a decimation filter of an analog-to-digital converter with ternary data encoding are presented. The filter reduces the clock frequency of the delta-sigma modulator of 100 MHz by a factor of 27. The proposed circuit engineering solutions are designed for manufacturing using the standard 0.18 μm MOS technology and the bipolar supply of ±0.9 V. The performance capability of the circuits is confirmed by the results of functional and circuit simulation using MatLab and Cadence Design Systems software.     

A 0.5-V, 2-nW, 55-dB DR,fourth-order bandpass filter using single branch biquads: An efficient design for FoM enhancement

A compact nano-power fourth-order bandpass filter operating from a 0.5 V supply, with an adjustable center frequency ranging from 125 Hz to 16 kHz, is presented. The filter is constituted from cascadable second-order circuit cells that are realized by a network of three transistors and two capacitors comprising only one branch of bias current. The measurement results of the filter fabricated in a 0.18-μm CMOS IC process indicate that, for a 1 kHz center frequency, a dynamic range of 55 dB is obtained from 2 nW power consumption. These results lead to best figure of merit achieved when compared to other existing designs to date.     

应用于ΣΔADC的多级抽取滤波器面积有效实现方法

本文介绍了一种用于音频过采样模数转换器的多级抽取滤波器的面积有效实现方法。抽取滤波器的抽取倍数为256,通带波纹小于0.005dB,阻带抑制达到100dB。通带范围为0-20kHz,输出为48kHz的16比特信号。通过采用含RAM和ROM的面积有效架构,以及对一个运算周期中有效的指令调度,该抽取滤波器在XilinxFPGA上综合后仅使用了不到300个LUT和不到160个Slice。不同于串行或部分串行架构中运算速率通常大于输入采样速率的情况,该实现方法可使得运算速率和采样速率一致,从而简化整体ΣΔADC设计并降低功耗。架构中RAM和ROM的采用使得该抽取滤波器可编程,进一步可改进用于自适应滤波应用。最后,在Modelsim中的RTL仿真结果通过Matlab\Simulink程序进行了验证。     

Passive CCD resonator filters

Novel passive recursive CCD bandpass filters have been realized using standard two-level-polysilicon gate NMOS technology. A Chebyshev bandpass (w/SUB rel,/ /SUB 3/ /SUB dB/=3.1 percent) and a fully integrated CCD signal filter with an extremely narrow 3 dB bandwidth of 97 Hz (Q=1350) at 131.85 kHz center frequency were implemented by means of cascaded CCD resonators. The latter chip contains the necessary clock generation and biasing circuitry realized with dynamic circuit techniques to achieve low power consumption (40 mW per filter). Performing all filtering operations exclusively in the charge domain ensures filter passivity. An extremely stable center frequency and a bandwidth independently controlled by a capacitance ratio are the special advantages of such filters.     

基于LTC1068-200的低频带通滤波器设计

在蓄电池性能监测过程中,接收的信号都是比较微弱的低频信号,而且为了得到更多的信息,往往向蓄电池施加多个频率的激励。因此,设计带通滤波器以提高抗干扰能力,而且中心频率要可调。开关电容滤波器可实现低通、高通、带通和带阻滤波功能,而且中心频率可调节,文中采用了LTC1068-200开关电容滤波器集成模块进行电路设计,时钟频率由CD4046锁相环控制。仿真结果表明本文设计的滤波器通带宽度可以达到5 Hz,中心频率从10 Hz到1 kHz可调节,满足实际需要。     

数字锁相放大器的实现研究

基于DSP设计了一种采样频率可控的数字锁相放大器。针对数字锁相放大器对低通滤波器性能的要求,采用CIC和降采样的方法,实现了一种高效的窄带低通滤波器。测试结果表明,在采样频率为500kHz时,低通滤波器的通带截止频率可达0.5Hz;当输入信号幅度为5～150mV时,系统测试的相对误差小于0.5%;当输入信号幅度为1～50μV时,系统测试的相对误差小于2%;同时系统在1～120kHz的工作范围内,具有较好的一致性。     

A practical micropower programmable bandpass filter for use in bionic ears

Subthreshold Gm-C filters offer the low power and wide tunable range required for use in fully implantable bionic ears. The major design challenge that must be met is increasing the linear range. A capacitive-attenuation technique is presented and refined to allow the construction of wide-linear-range bandpass filters with greater than 1 V/sub pp/ swings. For a 100-200 Hz fully differential filter with second-order roll off slopes and greater than 60 dB dynamic range, experimental results from a 1.5-/spl mu/m, 2.8-V BiCMOS chip yield only 0.23 /spl mu/W power consumption; for a 5-10 kHz filter with the same specifications the power only increased to 6.36 /spl mu/W. Fully differential filters with first-order slopes had a dynamic range of 66 dB and power consumptions of 0.12 and 3.36 /spl mu/W in the 100-200 Hz and 5-10 kHz cases, respectively. We show that our experimental results of noise and linear range are in good accord with theoretical estimates of these quantities.     

A highly linear CMOS Gm-C bandpass filter with on-chipfrequency tuning

A fourteenth-order CMOS transconductance-C (G_m-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear G_m-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 V_pp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm ² and consumes 70 mW from a single 5 V power supply     

Double-split-electrode transversal filter for telecommunication applications

A novel structure for on chip tap weight implementation in CCD transversal filters is described which employs two splits in the CCD sensing electrodes to improve on the performance of the conventional single-split weighting technique. This greatly reduces the capacitance associated with the sensing nodes and consequently reduces the common mode signal, gain sensitivity, coefficient error, and clock noise pickup. Experimental results are presented which verify this improved performance. The results achieved for a 3.4-kHz low-pass filter clocked at 32 kHz show a signal-to-noise ratio of 86 dB with harmonic distortion of less than 0.3 percent.     

一种用于无线接收机的噪声整形可重构复数带通/低通滤波器的设计

A reconfigurable complex band-pass （CBP）/low-pass （LP） active-RC filter with a noise-shaping technique for wireless receivers is presented. Its bandwidth is reconfigurable among 500 kHz, 1 MHz and 4 MHz in LP mode and 1 MHz, 2 MHz and 8 MHz in CBP mode with 3 MHz center frequency. The Op-Amps used in the filter are realized in cell arrays in order to obtain scalable power consumption among the different operation modes. Furthermore, the filter can be configured into the 1st order, 2nd order or 3rd order mode, thus achieving a flexible filtering property. The noise-shaping technique is introduced to suppress the flicker noise contribution. The filter has been implemented in 180 nm CMOS and consumes less than 3 mA in the 3rd 8 MHz-bandwidth CBP mode. The spot noise at 100 Hz can be reduced by 14.4 dB at most with the introduced noise-shaping technique.