片上网络容错路由算法分析和评价

片上网络技术是借鉴并行分布式计算机及传统计算机网络的概念解决片上多核系统的通信问题.片上网络代替片上总线通信,解决了片上总线结构所引起的可扩展性、效率、面积、功耗等问题.然而,片上网络在数据传输过程中可能由于各种原因产生故障,因此片上网络可靠性研究是当前一个研究热点.首先总结了片上网络故障分类,比较和分析了当前片上网络...     

基于共享缓存的三维片上网络的功耗建模及分析

片上网络是为应对未来片上通信架构各种挑战而提出的一种新型解决方案。三维芯片技术相对于二维结构可以实现更高的集成度,更优越的性能,如混合集成和低延时。用于垂直互联的硅通孔技术,可以降低水平长互联线的长度,进而实现低延时、低功耗。本文根据具体的硅通孔的电容模型建立了三维网状片上网络的功耗模型。该模型可用于片上网络设计早期阶段的评估,实现快速的功耗预测。本文根据具体的尺寸信息选择了两种三维网状片上网络结构,分别具有一层和两层存储单元。仿真结果表明,在注入率为0.35的情况下,两种三维网状片上网络与传统的二维网状片上网络相比,功耗分别降低了14%和26.96%。     

异步式逻辑保障片上网络传输可靠性的研究

随着Si技术的持续发展,片上系统(SoC)的规模和复杂度的增长给传统的片上互连,如总线结构,带来了前所未有的挑战。片上网络[1-2]是片上系统的一种新设计方法,是目前公认应对这种挑战较为有效的解决方案。半导体工艺进入深亚微米时代后,片上网络的可靠性也越来越成为人们关注的问题。将在研究如何应用异步式逻辑保障片上网络互连数据传输的可靠性和服务质量,提出了一个异步式片上网络的架构。通过实验证明,异步式逻辑将极大提高集成电路在应对电源不稳定性、导线间串扰、电磁干扰(EMI)、时钟偏斜和软错误方面的可靠性。采用全局异步局部同步的时钟机制,该方法带来了一种全新的片上通信方法,显著改善了传统总线式系统的性能。     

SoC设计中的片上通信体系结构研究

以超深亚微米工艺和IP核复用技术为支撑的系统芯片(SoC)技术,是目前超大规模集成电路和嵌入式电子产品设计的主流.SoC中各IP核之间的片上通信体系结构是SoC设计关键技术之一,同时对SoC的性能起着至关重要的作用.提出一种SoC中的混合片上通信体系结构,该体系结构将传统的共享总线与片上网络相结合,既保留了片上共享总线面积小的优点,又具有片上网络的并行通信的优点.此外,该混合片上通信还可以扩展到二维网络.     

片上网络关键技术及仿真方法研究

片上网络(NoC)的研究借鉴了计算机网络的设计思想,将计算机网络技术移植到芯片设计中来.介绍了片上网络的关键技术和仿真方法,包括拓扑结构、路由与交换协议、流量控制、缓存设计、性能评估与仿真等,并对今后的研究做出了展望.     

片上网络IP提供商：Sonics

近日,Sonics公司以＂片上网络IP提供商＂的角色进入业内媒体的视野。所谓＂片上网络＂听起来比较抽象,其实就是SoC上各处理器和存储器间的通信网络。而＂片上网络IP提供商＂则是专门提供片上网络技术IP的公司。现在半导体产业的分工日益精细。象这样的片上网络技术,原本应是SoC厂商自己要做的事情,现在都有专门的公司来提供专门的解决方案。     

面向未来移动通信终端的片上网络设计

随着通信技术和集成电路技术的飞速发展,功能越来越强的移动通信终端产品层出不穷。未来移动通信终端不仅要支持更高的数据传输速率,而且要融合更多的功能,同时还要支持多协议以实现无缝接入。这些特征要求使得未来移动通信终端片上系统需要集成更多的IP核,同时对IP核之间的通信协作效率要求更高。当前片上系统广泛使用的总线结构已经无法满足未来移动通信终端的上述要求,取而代之的将是片上网络结构。片上网络具有较好的可扩展性、灵活性、以及可重用性,并且可以在IP核数目增加时保持良好的性能。本文重点介绍了面向未来移动通信终端片上网络设计的几个关键技术,包括设计目标和约束条件、拓扑结构、布局、仿真等。根据这些关键技术,本文总结了面向未来移动通信终端的片上网络设计流程,详细阐述了各关键技术之间的相互关系,最后用一个例子来对该设计流程进行具体说明。     

三维片上网络拓扑研究

三维片上网络是集成电路领域的新技术,用于解决目前片上系统集成度越来越高所面临的通信瓶颈.本文介绍了当前三维片上网络的拓扑和相关技术,提出了三种新型的基于De Bruijn图的拓扑,并对各种拓扑的性能参数进行了比较.     

基于大数据技术的片上网络静态漏洞检测系统研究

为减轻静态漏洞体对计算机片上网络造成的序列化运行危害,设计一种基于大数据技术的片上网络静态漏洞检测系统。利用Hadoop检测框架,定向规划片上网络漏洞处理模块、静态漏洞评估模块的物理运行位置,实现新型检测系统的硬件运行环境搭建。在此基础上,采集漏洞信息的入侵行为,并以此为标准编写大数据检测函数,在相关组织设备的促进下,构建片上网络的静态漏洞行为链,实现新型检测系统的软件运行环境搭建。结合基础硬件条件,完成基于大数据技术的片上网络静态漏洞检测系统研究。对比实验结果显示,与hook系统相比,应用新型漏洞检测系统后,计算机片上网络的平均容错率达到90%,单位时间内出现的漏洞总量不超过3.0×109TB,序列化运行危害得到有效缓解。     

片上网络交换机制的研究

随着半导体技术进入超深亚微米时代,人们已经可以将越来越多的器件集成到单一芯片上来。运用传统的片上总线结构进行通信将面临诸多问题,如可扩展性差、定时困难和无法提供并行通信能力等,所以要运用片上网络来满足片上通信的带宽和能耗要求。本文研究了片上网络中的一项关键技术——交换机制。交换机制定义了消息在网络中交换的方式,并规定了沿输出端口将消息转发出去的时机。文章对片上网络中常用的电路交换、分组交换、虫孔交换和虚切通交换等进行了分析,并从能耗、面积、时延以及吞吐等性能方面进行了对比,给出了有益于片上网络沿用的结论。     

片上网络节点编码的设计和在路由方面的应用

网络拓扑选择和路由算法设计是片上网络设计的关键问题.在比较现有的三种网络拓扑结构的基础上,提出了一种隐含着相邻节点以及节点之间链路关系并适合二维Torus拓扑结构的节点编码方法.该编码和Torus结构的结合能拓扑结果够简化路由算法的设计和实现,改善了网络路由性能.实验结果表明,提出的编码方法与二维Torus拓扑结构的结合有效地提高了片上网络通信性能.     

An adaptive congestion-aware routing algorithm based on network load for wireless routers in wireless network-on-chip

Wireless Network-on-Chip (WiNoC) is regarded as one of the promising alternative approaches for sorting out the issues of latency and power consumption in the conventional Network-on-Chip (NoC). Despite the additional bandwidth of wireless channels on a chip, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and the shared use of these channels among all the cores. In this paper, an adaptive congestion-aware routing algorithm consistent with traffic load is proposed for solving the congestion problem of WRs. The proposed algorithm selects source-destination pairs with the longest wired hop distance for using wireless channels. The number of selected packets is determined based on the wireless channel bandwidth and the network traffic load. Simulation results show up to 65% latency improvement, 16% wired/wireless link utilization improvement and a saturation throughput increase of approximately 11%.     

3D NoC测试规划研究与实现

针对3D NoC资源内核的测试,采用NoC重用测试访问机制和XYZ路由方式,建立功耗模型,并通过云进化算法将IP核的测试数据划分到各TAM上进行并行测试,从而降低了测试时间。实验以ITC 02标准电路作为测试对象,其结果表明,文中方法可以有效地减少测试时间,提高了测试效率。     

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.     

Statistical estimation and evaluation for communication mapping in Network-on-Chip

In order to exploit the advantages in on-chip communication introduced by Network-on-Chip, many optimization algorithms have been proposed for a joint optimization on power and performance in communication mapping and routing. However, the optimality of solutions relative to these algorithms has been neglected in previous studies. To this problem, this paper proposes an early estimating approach to evaluate the optimality of the solutions for the first time. This approach is based on a statistical property that the overall solutions in solution space conform to a quasi-Gaussian distribution, which can be previewed by two parameters with a computation complexity of O(n⁴) as presented. The generality of our proposed approach makes itself extensible to other on-chip network options. Experiments on real and synthetic application benchmarks demonstrate an average error ratio less than 7% which tends to be even smaller when problem scales up. These results validate our early estimating approach on optimality evaluation as credible and efficient to boost its utility in the promising Network-on-Chip design.     

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network-on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based design.     

A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation

Mapping IP cores to an on-chip network is an important step in Network-on-Chip (NoC) design and affects the performance of NoC systems. A mapping optimisation algorithm and a fault-tolerant mechanism are proposed in this article. The fault-tolerant mechanism and the corresponding routing algorithm can recover NoC communication from switch failures, while preserving high performance. The mapping optimisation algorithm is based on scatter search (SS), which is an intelligent algorithm with a powerful combinatorial search ability. To meet the requests of the NoC mapping application, the standard SS is improved for multiple objective optimisation. This method helps to obtain high-performance mapping layouts. The proposed algorithm was implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show that this optimisation algorithm achieves low-power consumption, little communication time, balanced link load and high reliability, compared to particle swarm optimisation and genetic algorithm.     

Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching

Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel partitioned NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield high performance in terms of latency and throughput, while still offering a cost-effective implementation.     

Routing for reliable manufacturing

The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based on this analysis, a general routing cost function is presented, in which the manufacturability of a net is taken into account in conjunction with traditional routing objectives. The new cost function, relating the process spot defects to the routing procedure has been implemented. Failure probabilities are analyzed for the benchmark layouts obtained by our routing tool using both the original cost function and the new cost function. The results show that the failure probability of a layout is significantly decreased if the spot defect mechanism is taken into account in the routing procedure, while the area of the layout is kept constant