基于热测试芯片的2.5D封装热阻测试技术研究

2.5D多芯片高密度封装中,多热源复杂热流边界、相邻热源热耦合增强,高精准的热阻测试与仿真模拟验证是封装热设计的关键。设计开发了基于百微米级发热模拟单元的热测试验证芯片（TTC）,并基于多热点功率驱动电路系统和多通道高速采集温度标测系统,实现了2.5D多芯片实际热生成的等效模拟与芯片温度的多点原位监测。通过将实际热测试结构函数导入热仿真软件,实现了仿真模型参数的拟合校准,采用热阻矩阵法表征多芯片封装热耦合叠加效应,实现了多热源封装热阻等效表征。结果表明,多芯片封装自热阻和耦合热阻均随着芯片功率密度的增加而提高,芯片的热点分布对封装热阻值的影响更为显著,因此模拟实际芯片发热状态、建立等效热仿真模型是实现高精准封装热仿真和散热结构设计的关键。     

热阻网络法在半导体照明光源热分析中的应用

热阻网络法在传统热阻定义的基础上,简化了系统的计算模型。文章在分析半导体照明系统内部各器件热阻的基础上,提出了一种计算各点温度的热阻网络模型。利用一维热阻网络拓朴关系进行了热场的计算和分析,并与有限元仿真结果进行了对比。通过验证表明,采用该方法得到的结点温度与有限元仿真的结果相差不超过5%,模拟结果与热阻网络模型预测的结果吻合得很好,显示该模型具有较高的精确度。这种热阻网络拓朴分析技术可在某种程度上应用于发光二极管(LED)组件甚至复杂的照明系统的热学分析。     

温度对压接型IGBT器件内部接触热阻的影响

温度是功率半导体器件备受关注的问题,不仅直接影响功率半导体器件的电气性能,而且还间接影响功率半导体器件的热学和机械特性.压接型IGBT器件内部是电磁场、温度场和结构场的多物理量耦合场,器件内部各组件间的接触热阻是温度场与结构场双向耦合的重要桥梁,也是器件可靠性的重要影响因素.通过单芯片子模组有限元模型分析了各组件间的接触热阻,重点研究了温度对接触热阻的影响,计算了热阻测量前后的接触热阻值,并进行了对比.鉴于目前接触热阻测量方法的局限性,通过测量单个快恢复二极管(FRD)芯片子模组结到壳热阻值与温度的变化关系间接得到接触热阻与温度的关系,并对有限元计算结果进行了验证.     

建立封装芯片热阻网络模型的方法研究

针对电子设备系统级热分析中封装芯片模型复杂程度与计算精度的矛盾,引入热阻网络法,替代系统级分析中封装芯片的详细物理模型;并以某PBGA封装芯片为例,进行两种建模方法的对比分析,同时介绍一种快速确定网络中热阻值的方法.结果表明,热阻网络等效方法具有模型简单、分析快速、准确度高的优点,在系统级热分析中可完全替代详细的物理模型.     

接触热阻的计算及ICEPAK环境下的数值模拟

为解决通信装备大功率芯片与散热器之间接触热阻的难以估算的现实问题,从粗糙表面的微观数学描述入手,采用截锥体的粗糙峰形状论述粗糙表面的数学模型,并结合接触分热阻理论建立了接触热阻的计算模型。为便于实际应用,对该计算模型进行了工程简化;应用ICEPAK软件结合粗糙表面的数学模型建立了热仿真模型,并对四个工况的接触热阻进行数值模拟,通过对比简化模型和数值模拟的计算结果表明:在通常情况下简化模型对于预测接触热阻具有一定的工程实用价值。     

手持式干扰机的傅氏级数热布局优化

针对手持式干扰机热布局的需要,利用傅里叶级数对影响热阻的因素进行优先级划分,通过芯片对热阻值影响的优先级依次对芯片进行布局,得到手持式干扰机电路板上芯片的最优布局方案。利用有限元分析软件ANSYS对最优布局方案进行仿真,结果表明,通过利用傅里叶级数对手持式干扰机电路板上的芯片进行优化布局,手持式干扰机的热阻值减小,散热变快。芯片的最高温度降低了4.75%,可靠性得到了提高。     

脉冲螺线行波管热状态分析及ANSYS模拟

本文对国外上世纪90年代的产品,高输出功率高工作比的脉冲行波管进行热状态的分析,通过计算全面了解国外行波管的热设计要求及必要的工艺措施,为国内同类型行波管提高可靠性服务.文中对国内同类型产品的表面热阻率进行测量,从初步分析结果指出减小表面热阻率的方向和措施.使用ANSYS软件实际模拟仿真螺线行波管,得到更为准确、可靠的结果,并和设计计算基本保持一致.     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

半导体薄片激光器窗口散热模式的热效应

基于垂直外腔面发射半导体激光器窗口散热模式的传热模型,用有限元法计算了不同条件下量子阱有源区的温度变化,建立了量子阱最高温度的等效热阻模型和计算公式,并通过拟合确定了热阻模型的相关参数.计算表明量子阱最高温度与抽运功率存在线性关系,与光斑面积近反比关系,窗口散热片可显著降低量子阱有源区温度和温度的不均匀度.等效热阻模型表明由于半导体晶片内热流在径向难以扩散,热传导中存在较大串联热阻,使得散热片热扩散能力趋于饱和,其中碳化硅的散热性能约为金刚石的75%.     

X波段T/R组件功率放大器芯片的热设计

针对X波段T/R组件中的功率放大器芯片,建立芯片热模型,给出了获取器件热阻的公式和方法,并对功放芯片的等效热路进行了分析计算.文中给出了常用材料的热导率,对不同壳底材料,求出了在确保功放可靠工作下的系统最大热沉温度,从而为组件设计师优化组件成本提供了依据.最后提出了提高功率芯片可靠性的建议.     

有关QFN72和CQFN72的热阻计算

文章介绍了QFN72和CQFN72结到外壳的等效热路分析及结到外壳热阻θJC的简化计算方法,结果表明原设计下CQFN72的热阻约为1.25 K·W-1,几乎是QFN72的一倍。优化CQFN热设计的主要途径是适当减薄陶瓷基板厚度、在陶瓷基板中嵌入钨柱阵列、芯片减薄和采用金基焊料焊接等。从CQFN热设计考虑,不应在主散热区热沉下采用4J29或4J42焊接垫片,否则会使热阻θJC增大10%以上。     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

CMOS门阵列电路用封装外壳的研制

介绍了一种用于封装万门至十万门级ＣＭＯＳ门阵列电路的ＰＣＡ１３２多层陶瓷外壳的研制。该外壳的设计采用了ＣＡＤ设计布线,模拟并优化外壳的信号线电阻、线间电容、电感及传输延迟等参数,使其满足电路要求。并且通过结构可靠性设计,使外壳抗机械冲击、温度冲击能力大大提高,满足了高可靠应用要求。     

DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.     

Heat transfer analysis of beam-lead transistor chip

The program package which is applicable to solve problems of heat transfer in transistors or integrated-circuit chips or in their stems has been developed with a three-dimensional lumped network model. The thermal resistances of beam-lead transistors calculated with this program are found to be in good agreement with the observed values. For the better design of beam-lead devices, thermal resistances are evaluated with this program for various geometries of the chips and for the passivation films of 1-micron thick SiO2, 2-micron SiO2, and 0.2-micron Al2O3or Si3N4on 1-micron SiO2. The results calculated indicate that the thermal resistance is mainly dependent on the thickness of electroplated Au in the beam-lead structure, and that the heat dissipation is especially sensitive to the distance, which is measured along the beam lead from the chip edge to the nearest end of the joining part of the beam lead to the metallized conductor on the ceramic stem.     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

Steady state thermal characterization and junction temperatureestimation of multichip module packages using the response surfacemethod

The steady state thermal performance of semiconductor packages has been traditionally reported through the utilization of a single junction-to-ambient thermal resistance constant commonly referred to as &thetas;_ja. This is particularly inadequate for multichip modules where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multichip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual integrated circuit devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit     

Developing a Simplified Analytical Thermal Model of Multi-chip Power Module

The study of the thermal behavior of power modules has become a necessity regarding the known rapid development in modern power electronics, and the prediction of temperature variation has generally been performed using transient thermal equivalent circuits. In this paper we have developed a simplified analytical thermal model of a power hybrid module. This analytical method is used to evaluate the thermal parameters of a device. The model takes into account the thermal mutual influence between the different module chips based on the analytical method. The thermal interaction between components is dependent on the boundary condition, the dissipated power value in the different components and the number of operating chips constituting the module. This effect is modelled as a source energy and a thermal resistance simply computed tanks to reasonably low measurement applied on the module. The derived thermal models offer an excellent trade-off between accuracy, efficiency and CPU-cost.