数字电路中NBTI效应仿真及建模方法的研究

负偏压温度不稳定性(NBTI)效应已成为影响数字电路设计的重要可靠性问题之一。首先讨论了PMOS晶体管中NBTI效应对数字电路的影响,提出针对不同工艺PMOS管中NBTI效应建模的流程,设计了一种基于SPICE模型的NBTI仿真模型。该模型能够通过Cadence软件调用,并在实际的数字电路设计中进行动态仿真,预测NBTI效应对电路性能的影响。基于该建模流程,在Cadence软件中对基于40 nm工艺的一级两输入与非门和四十级反相器组成的环形振荡器进行仿真。仿真结果表明,该模型能够对不同工艺下PMOS管中的NBTI效应进行准确、有效地仿真,为数字电路的可靠性设计提供保障。     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

On the Formation of Positive Charges in Ultrathin Silicon-Oxynitride p-MOSFETs Subjected to Negative Bias Temperature Stress

p-MOSFET negative bias temperature instability (NBTI) has become the most important reliability issue for the CMOS industry. This letter investigates the formation of oxide positive charges (PCs) and its effects on the NBTI. Evidence shows that PC dominates NBTI at stress temperature lower than 373 K, whereas interface-state generation has an obvious contribution above 373 K. Two kinds of PC are distinguished as follows: The trapped holes are the main origin of NBTI at lower temperatures, and the generated PC plays a role at higher temperatures. The physical mechanisms of the two kinds of PC are also discussed in this letter.     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

NBTI机制下运算放大器的性能退化分析及其可靠性设计

随着CMOS器件尺寸的不断缩小,集成电路设计阶段的可靠性问题变得愈加重要,NBTI效应作为重要的可靠性问题之一得到了大量的研究,并从电路级对其提出了改进。采用等效电路模型表征NBTI退化对模拟电路的影响,研究了两级运算放大器在NBTI效应影响下电路参数的退化,分析并确定了影响传统两级运算放大器性能的关键器件。在此基础上,对传统运放结构进行改进,引入反馈,使-3dB带宽的退化量由27%降到了1%左右,从而减小NBTI退化对电路性能的影响。     

The negative bias temperature instability in MOS devices: A review

Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted.     

Analysing NBTI Impact on SRAMs with Resistive Defects

Density’s increase in Static Random Access Memory (SRAM) has become an important concern for testing, since new types of defects, that may occur during the manufacturing process, are introduced. On the one hand, new manufacturing defects may lead to dynamic faults, which are considered one of the most important causes of test escape in deep-submicron technologies. On the other hand, the SRAM’s robustness is considered crucial, since it may affect the entire SoC. One of the most important phenomena to degrade SRAM reliability is Negative-Bias Temperature Instability (NBTI) causing the memory cells’ aging. In this context, the paper proposes to analyse the impact of NBTI on SRAM cells with resistive defects that eventually escape manufacturing test and, with aging, may generate faults over time. Finally, SPICE simulations adopting a commercial 65 nm CMOS technology library have been performed in order to estimate NBTI’s precise impact over time.     

PMOS NBTI-induced circuit mismatch in advanced technologies

PMOS transistor degradation due to negative bias temperature instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular importance for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS-NBTI induced mismatch on analog circuits in a 90 nm technology.     

负偏置温度不稳定性导致单粒子瞬态脉冲的压缩与展宽

摘要：本文基于3D TCAD 器件模拟,研究了130nm体硅工艺下,负偏置温度不稳定性（NBTI）对单粒子瞬态（SET）脉冲的影响。研究结果表明：当粒子轰击高输入反相器的PMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断压缩,当粒子轰击低输入反相器的NMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断展宽。基于研究结果,本文首次提出：NBTI对粒子轰击NMOS管所产生的SET脉冲的影响已经十分严重,在进行抗辐照加固设计时必须考虑NBTI所造成的影响。     

嵌入式高速ADC的最新研究进展

随着数字化程度的不断深入,系统级芯片（SoC）已成为当前发展主流,系统芯片对高速高精度嵌入式ADC的需求日益迫切。CMOS工艺尺寸的等比例缩小为ADC速度的提高提供了条件,但是对实现ADC高信噪比的限制越来越大。文章首先讨论了CMOS工艺尺寸的不断等比例缩小对ADC性能的影响,其次讨论了采用数字电路进行纠错补偿、省略运算跨导放大器（OTA）使用以及采用电流域信号处理技术等适用于嵌入式高速ADC设计的最新技术进展。     

深亚微米CMOS器件可靠性机理及模型

随着CMOS集成电路特征尺寸的不断缩小,特别是在其发展到深亚微米阶段之后,CMOS器件面临着负偏置温度的不稳定性、栅氧化层经时击穿、互连系统的电迁移和热载流子注入等可靠性问题。重点对近年来研究得到的深亚微米CMOS器件可靠性机理及其可靠性模型进行了总结。     

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.     

Study for pulse stress NBTI characteristics degradation stress

NBTI characteristic degradation of MOSFET is still one of important reliability physics in semiconductor device. Although it is well recognized that its degradation is recovered immediately after releasing DC test stress, it is also fact that the voltage which is applied to the gate electrode in most semiconductor device is an intermittent stress like pulse, not consecutive DC stress as NBTI test. Accurate NBTI lifetime prediction method under this pulse stress condition can afford an actual reliable lifetime. In this work, we considered the characteristic recovery phenomenon in pulse NBTI stress with MOSFET of TOSHIBA 40 nm and 90 nm CMOS process technology and examined a more realistic life prediction method.     

Negative bias temperature instability induced single event transient pulse narrowing and broadening

The effect of negative bias temperature instability(NBTI) on a single event transient(SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations.The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter;but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter.Based on this study,for the first time we ...     

From defects creation to circuit reliability - A bottom-up approach (invited)

This paper presents a theoretical framework about interface states creation rate from Si-H bonds at the Si/SiO₂ interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability - CMOS device reliability in this case - at design stage thereby enabling judicious margins to be taken beforehand.     

A comparative study on performance and reliability of 32-bit binary adders

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

Engineering of nitrogen profile in an ultrathin gate insulator to improve transistor performance and NBTI

During evaluation of negative bias temperature instability (NBTI) in short-channel devices, we found that using an optimized nitrogen depth profile is important in suppressing NBTI when scaling down CMOS devices. Performing the NO anneal process before oxidation yeilds good transistor performance, suppressing NBTI by 25%. When using more nitrogen to moderate gate leakage and boron penetration, in addition to the amount of nitrogen, it is important to control the depth profile of the nitrogen on the gate insulator, as our research shows that the interface peak concentration of nitrogen enhances NBTI degradation.     

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

CMOS latchup and electrostatic discharge (ESD) continue to be a semiconductor quality and reliability area of interest as semiconductor components continue to be reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, CMOS latchup and ESD robustness will continue to be a technology concern. With both the revolutionary and evolutionary changes in CMOS and Silicon Germanium semiconductor technologies, and changing product environments, new CMOS latchup and ESD requirements also continue in semiconductor design, device and chip-level simulation, design verification, chip-to-system evaluation, and the need for new latchup and ESD test specifications. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of latchup and ESD. Although latchup and ESD are not a new reliability arena, there are also new issues rising each year, making the latchup and ESD an area of continuous discovery, innovation and invention. In this paper, an introduction to latchup in CMOS and BiCMOS Silicon Germanium will be discussed.     

PMOSFET动态NBTI效应的研究

负偏压温度不稳定性效应(NBTI)已经成为影响CMOS集成电路可靠性的一个关键因素,而动态应力条件下的NBTI效应对器件和电路的影响越来越受到关注。对PMOSFET的动态NBTI效应进行了系统介绍,讨论了动态应力条件下NBTI(DNBTI)效应和静态应力下NBTI(SNBTI)退化机理,综述了DNBTI效应的动态恢复机制以及影响因素,最后介绍了NBTI效应对电路的影响。随着器件尺寸的日益缩小,如何提高电路的可靠性变得日益重要,进一步研究NBTI效应对电路的影响从而进行NBTI电路级可靠性设计已成为集成电路设计关注的焦点。