倒装芯片封装中非牛顿流体下填充的数值仿真

倒装芯片封装中的下填充工艺可以有效地提高封装连接的可靠性,因而得到了广泛应用。含有硅填料的环氧树脂是常用的下填充胶料,在下填充流动过程中表现出明显的非牛顿流体特性。利用Fluent软件对具有非牛顿流体特性胶料的下填充过程进行了三维数值模拟。采用流体体积比函数(VOF)对流动前沿界面进行追踪,再用连续表面张力(CSF)模型来计算下填充流动的毛细驱动力,并用幂函数本构方程来体现下填充胶料的非牛顿流体特性。通过数值模拟,获得了下填充流动前沿位置随时间变化的数据,这些数据与实验结果有较好的吻合度。该数值方法可较好地预测具有非牛顿流体性质胶料的下填充过程。     

基于表面能理论的倒装芯片封装下填充流动研究

为了预测倒装芯片封装中的下填充过程,通常要首先通过繁复的方法来求解平均毛细压.为了避免此问题,从能量的角度分析了倒装芯片封装工艺中的下填充流动过程.认为下填充是较低表面能的界面代替较高表面能的界面的过程,所释放的表面能用于形成流体流动的动能和克服阻力的能量损耗,期间能量守恒.在此分析的基础上建立了下填充流动的新模型.建立了可视化的下填充流动实验装置,并用下填充实验验证了所建立新模型的准确性.该模型避免了计算平均毛细压的复杂过程,并可方便地扩展到焊球排布形式不同的倒装芯片.     

倒装芯片封装中下填充流场渗透率的数值分析

倒装芯片封装中的下填充流场可以假设为多孔介质流场,其渗透率的求解对研究下填充流动过程至关重要。根据下填充流场所具有的周期性结构,通过单胞数值模拟的方法得到了下填充流场的渗透率。通过对渗透率数据的分析,发现了渗透率和下填充流场参数之间的关系,并建立了计算渗透率的幂律模型。其中幂律模型的底是下填充流场的孔隙率,系数仅与芯片和基板的间隙有关,指数仅与芯片和基板的间隙相对于焊球直径的比值有关。通过实例分析表明,与其他模型相比,用基于幂律模型的渗透率所计算出的填充时间更符合实验结果。     

球形焊点三角形排列倒装芯片底部填充的能量法研究

对于具有球形焊点且呈正三角形排列的倒装芯片,由于其待填充的空隙结构复杂,难以通过平均毛细压来建立底部填充的解析模型.因此通过能量变化来分析底部填充过程以避免平均毛细压的计算.首先分析了底部填充过程中表面能的变化、动能的变化和流道壁面对流动的阻力损耗;然后根据能量守恒定律得到了反映底部填充过程的新解析模型;最后用计算流体力学(CFD)软件对底部填充过程进行了三维数值模拟,以此验证了基于能量法的新解析模型.能量法更具有通用性,可用于研究焊点形状和排列方式复杂的倒装芯片底部填充过程.     

焊球正六边形排布倒装芯片的下填充毛细压研究

除了正四边形,正六边形也是倒装芯片中可行的焊球排布形式,为了预测封装倒装芯片时的下填充过程,需要精确计算毛细驱动压.在已有的焊球正四边形排布情况下平均毛细压计算方法的基础上,进一步研究了焊球正六边形排布情况下平均毛细压计算模型.通过分阶段处理,并根据质量守恒和力平衡的原则,分析了下填充过程,重点分析了填充面积和接触线跳跃量的计算,进而得到了计算平均毛细压的数学模型.通过实例验证了该模型的准确性,从而完善了倒装芯片封装工艺中的下填充流动解析模型.     

焊球分布模式对芯片下填充胶流动的影响

分析了在倒装芯片尺寸、相邻焊球中心之间距离相同的情况下,焊球点满布叉排排列和满布顺排排列对倒装芯片下填充流动的影响。并就焊球点布置密度不同,在顺排和叉排排列两种方式时,用相同的填充时间填充材料流动前端所走过的距离以及其分布情况进行了计算机模拟分析研究。     

倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

倒扣芯片连接焊点的热疲劳失效

测量了有无芯下填料B型和D型两种倒扣芯片连接器件的焊点温度循环寿命,运用超声显微镜(C-SAM)和扫描电镜(SEM)观察了焊点微结构粗化和裂纹扩展,并采用三维有限元模拟方法分析了焊点在温度循环条件下的应力应变行为.结合实验和模拟结果,建立了预估焊点疲劳寿命的Coffin-Manson半经验方程,得到方程中的系数C＝5.54,β=-1.38.模拟给出的焊点中剪切应变的轴向分布与实验得到的焊点在温度循环过程中的微结构粗化一致.填充芯下填料后的倒扣芯片连接由于胶的机械耦合作用,降低了焊点的剪切变形,但热失配引起的器件整体弯曲增强,芯片的界面应力增大.模拟结果与实验观察完全一致.     

倒扣芯片连接焊点的热疲劳失效

测量了有无芯下填料B型和D型两种倒扣芯片连接器件的焊点温度循环寿命,运用超声显微镜(C-SAM)和扫描电镜(SEM)观察了焊点微结构粗化和裂纹扩展,并采用三维有限元模拟方法分析了焊点在温度循环条件下的应力应变行为.结合实验和模拟结果,建立了预估焊点疲劳寿命的Coffin-Manson半经验方程,得到方程中的系数C＝5.54,β=-1.38.模拟给出的焊点中剪切应变的轴向分布与实验得到的焊点在温度循环过程中的微结构粗化一致.填充芯下填料后的倒扣芯片连接由于胶的机械耦合作用,降低了焊点的剪切变形,但热失配引起的器件整体弯曲增强,芯片的界面应力增大.模拟结果与实验观察完全一致.     

Numerical Modeling for the Underfill Flow in Flip-Chip Packaging

In the prediction of underfill flow in a flip-chip package, numerical methods are usually used for flow analysis and simulation since analytical methods cannot meet the requirement for predicting fluid distribution in a planar analysis. At present, there appears to be no simulation software commercially available that is able to provide adequate prediction for the underfill flow process driven by capillary force in a micro-cavity situation. In the study presented in this paper, a numerical model was proposed for the prediction of flip-chip underfill flow. In this model, the power-law constitutive equation was used to describe the non-Newtonian behavior of encapsulant fluids and a time-dependent velocity boundary condition was used instead of the pressure boundary condition commonly used. The comparison between the model-predicted and experimental results indicated that this model can give a good prediction for the underfill flow in a micro-cavity. This model was implemented by a general-purpose commercially available software program ANSYS, which has a high reliability and wide accessibility.      

军用倒装焊器件底部填充胶选型及验证方法讨论

从分析倒装焊器件底部填充的必要性入手,对底部填充胶的选型流程、选型基本方法及重点参数匹配情况进行了分析,优选出4款底部填充材料。通过对4款材料关键参数的理论计算及恒定加速度、热力学耦合仿真计算,优选出一种材料作为样本材料。同时对底部填充材料验证内容进行了梳理,通过试验验证摸索出材料的适用范围及边界条件。该底部填充胶的选型验证方法对于军用混合集成电路其他聚合材料的选型具有一定的指导意义。     

A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill

A computational survey was performed to evaluate the effect of volume and material properties on a concurrent underfilling and solder reflow manufacturing technique applied to flip-chip technology. Fillet geometry in addition to collapsed solder ball geometry and forces during solder reflow in the presence of liquefied underfill are reported. Targeted material properties included surface tension, wetting angles, and process parameters such as underfill volume. A regression model is presented representing over 1000 case studies completed using surface evolver. Also, a multiple ball model was developed to study the solder ball array behavior. Modeling results are presented. Application of this model for wafer applied coating underfill thickness prediction was also studied including the fillet forces added to a multiple-ball-model. Behavior and force studies combining all these effects were performed and are presented. Finally, a more realistic arrangement consisting of circular and square solder pad geometries combined is modeled for a single ball. The models results are expanded to include a multiball model employing a commonly used regression method. Solder joints were cross-sectioned and measured after reflow in the presence of a fluxing underfill for comparison to model predictions. The experimental results agree within 1.5%.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

An Analytical Model for Predicting the Underfill Flow Characteristics in Flip-Chip Encapsulation

This article describes an analytical model for the prediction of the underfill flow characteristics in a flip-chip package driven by capillary action. In this model, we consider non-Newtonian fluid properties of the encapsulant as opposed to most other studies where Newtonian fluid properties were assumed for the underfill flow. The power-law constitutive equation was applied in our study. The simulation based on this model agreed well with the measurement obtained from the experiments available in literature. It was further shown that this model performs better than the Washburn model traditionally used for the prediction of underfill flow characteristics in the flip-chip packaging. Based on this model, the effects of the solder bump pattern (including bump pitch, solder bump diameter, and gap height) on the process variables (i.e., flow front and filling time) were studied, which facilitated both the package design and the process optimization.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.