A CMOS line driver for ADSL central office applications

An ADSL central office (CO) line driver utilizing a single 6-V supply is described. The line driver output produces a 20-V/sub ppd/ signal to deliver a 40-V/sub ppd/ swing to a 100-/spl Omega/ line. The adoption of an active termination, a dynamic supply control circuit technique, and deep n-well devices at the output stage of the line driver is key in achieving such a large voltage swing in a 0.25-/spl mu/m CMOS process. In order to ensure reliability of the output devices, the dynamic supply control algorithm is designed to activate only one lift amplifier at each signal path of the differential line driver at any given time. A transformer turns ratio of 1:2.4 ensures both reliability and optimal power dissipation in the presence of system losses. The total power dissipation of the line driver is 700 mW when discrete multitone signals with a crest factor of 15 dB were used to deliver 20.4 dBm to a 100-/spl Omega/ line.     

A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm² and dissipates 450 mW from a 3.3-V supply     

A 610-mW zero-overhead class-G full-rate ADSL CO line driver

With the drive to increase the number of ports that can be incorporated onto a single linecard in an ADSL Central Office (CO), and the consequent power consumption and thermal management issues that this increased density raises, power dissipation is a key parameter in the design of an ADSL modem. This paper presents a full-rate ADSL CO line driver, consuming 610 mW through active termination and a zero-overhead class-G technique. The supply switching scheme used features very low overhead voltage, logic control, and controlled supply rail ramp rate, and requires analog signal peak prediction be done on the digital data stream. The process used features dielectrically isolated silicon-on-insulator 0.7-/spl mu/m complementary BiCMOS with thin-film resistors. The MOSFET class-G transistors operate in two modes for power efficiency and distortion control. The power consumption is 610 mW and the downstream missing tone power ratio is 69 dBC with 16-dB peak-to-average ratio support.     

Analog line driver with adaptive impedance matching

A new principle for an adaptive line driver is presented. This type of line driver can adapt its output impedance automatically to the applied load. This results in automatically corrected output impedance for different cables with terminations. Also, the line-driver output impedance becomes insensitive to process variations. As an example, a line driver for analog video signals has been designed. The circuit operates from a 2.4-V supply in a 0.35-μm CMOS technology. The realized circuit adapts between 38 and 85 Ω loads, has total harmonic distortion of <-50 dB at 1.2 V_pp for 0-10 MHz, 0.09-mm² area, and 9-mW static power consumption     

无源UHF RFID电子标签模拟前端设计

提出了一种符合ISO/IEC 18000-6B标准的高性能无源UHF RFID电子标签模拟前端,在915MHz ISM频带下工作时其电流小于8μA.该模拟前端除天线外无外接元器件,通过肖特基二极管整流器从射频电磁场接收能量.该RFID模拟前端包括本地振荡器、时钟产生电路、复位电路、匹配网络和反向散射电路、整流器、稳压器以及AM解调器等.该芯片采用支持肖特基二极管和EEPROM的Chartered 0.35μm 2P4M CMOS工艺进行流片,读取距离大于3m,芯片面积为300μm×720μm.     

ADSL调制解调器驱动器的实现

ADSL接入技术已成为终端用户最主要的宽带接入技术.ADSL技MODEM.ADSL用户端调制解调器驱动器是一个宽频带功率放大器,他能不失真放大和传输电话线上已编码的数字信号.本文通过对ADSL调制解调器驱动器特点、结构和性能的分析,给出了一种ADSL用户端MODEM驱动器的实现电路.该电路采用具有优良高频的双功率放大器LT1886,即使在配置高电平的闭环增益网络后也能保持较低的失真.     

A CMOS 5-V analog front end for 9600-bit/s facsimile modems

A CMOS 9600-b/s facsimile-modem analog front end was designed with the consideration that it be capable of being fabricated on the same chip with digital signal processing circuits. To achieve the dynamic range required in the high-speed QAM (quadrature amplitude modulation) modem environment with a single 5-V power supply, a fully differential architecture is used. The die area is 23 kmil/SUP 2/ and the power consumption is only 35 mW. The experimental results show that 76-dB dynamic range is achieved from the fully differential bandpass filter. The zero crossing detector in the MF-1 detection block can normally operate with -50-dBm input signal.     

Highly efficient xDSL line drivers in 0.35-/spl mu/m CMOS using a self-oscillating power amplifier

The design of two highly efficient line drivers in a digital 0.35-/spl mu/m, 3.3-V technology are presented. The self-oscillating power amplifier (SOPA) architecture has been developed in order to obtain a high efficiency for systems with a high crest factor like discrete multitone modulated xDSL modems. The SOPA architecture is an unclocked switching-type line driver. By using self-oscillation and noise-shaping, a high signal linearity can be obtained for low over-switching ratios. By coupling two SOPA line drivers with a signal transformer, the two limit cycle oscillations are pulled toward synchronization. This gives an important mean switching frequency suppression toward the line. The need for an extra filter dealing with the mean switching frequency is in that way heavily relaxed. A zeroth-order SOPA and a third-order SOPA are prototyped. The zeroth-order line driver meets ADSL-Lite specifications with a missing tone power ratio (MTPR) of 41 dB for an 800-kHz bandwidth. The maximum efficiency is 41%. The third-order version meets ADSL and VDSL specifications with an MTPR of 56 dB and an 8.6-MHz bandwidth. An efficiency of 47% was measured for an ADSL signal with a crest factor >5.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driverfor Ethernet and fast Ethernet networking applications

A fast line driver has been developed for networking applications in a 0.4-μ digital CMOS process. It is intended to drive cables with large, low-distortion sinewaves for 10BASE-T and sharp-edged pulses for 100BASE-T-type data communications. The driver has a fully differential architecture and uses a current-feedback approach to achieve small- as well as large-signal closed-loop bandwidths in excess of 100 MHz. It can drive a 10-MHz, 5-V_pp sinewave across a 50-Ω load from a 3.3-V power supply with a total harmonic distortion of -43 dB. The quiescent power consumption of the driver is 25 mW, while its area is 0.15 mm²     

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-μm 45-GHz f_T SiGe BiCMOS process     

A 3.3-V CMOS adaptive analog video line driver with low distortion performance

An analog line driver for video applications is presented. Utilizing a class-AB error amplifier structure, the design achieved 1.2-V peak-to-peak output swing with better than 42-dB linearity for frequencies up to 5 MHz. An adaptive tuning scheme for output impedance matching using peak detection is used to provide uniform performance across line impedance variations. The circuit is designed in AMI 0.5-/spl mu/m CMOS technology and has a tuning range of 70-180 /spl Omega/ with a power consumption of about 26.4 mW at 75-/spl Omega/ load.     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

A monolithic IGBT gate driver for intelligent power modules implemented in 0.8 μm high voltage (50 V) CMOS process

This paper discusses the design and implementation of a monolithic IGBT gate driver for intelligent power modules (IPMs). The objective of this work is to design and implement a monolithic IGBT gate driver IC with efficient protection functions in a high-voltage (50 V) 0.8-μm CMOS process. The gate driver is designed for medium power applications, such as home appliances. It includes low-voltage logic, 5-V logic regulator, analog control circuitry, high-voltage (50 V) high-current output drivers, and protection circuitry.     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm²     

A 5-V CMOS programmable acoustic front-end for ISDN terminals anddigital telephone sets

A 5-V CMOS programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions, fulfilling all D3/D4 and CCITT specs. Moreover, it implements the main analog interfaces required for the speech channel (low-noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a four wire separated control interface or by means of a serial control channel multiplexed with the PCM voice/data channel in a GCI compatible format. Chip area is 30 mm ² in a 1.5-μm CMOS technology. The active/stand-by power consumption is 60 mW/0.2 mW from a single 5-V supply. All circuits are designed to meet performance objectives over a voltage range from 4.5 V to 5.5 V and a temperature range from -40°C up to 85°C     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

Low Power 260k Color TFT LCD Driver IC

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power‐lowering schemes in the logic and analog design. A driver IC for LCDs has a built‐in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row‐line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8‐transistor leaf cell and a 6‐transistor leaf cell. We propose an efficient scan method for a 6‐transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 µm process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.