一种多处理器原型及其系统芯片设计方法

 随着嵌入式应用快速发展,系统芯片(SoC)设计日趋复杂.高效可靠的设计多处理器系统芯片逐渐成为一个巨大挑战.本文提出一种多处理器原型及其SoC设计方法,将多处理器及其通信统一建模于一个多层次、灵活和可配的软硬件原型中,通过分层次、从高层抽象到底层实现逐步深入的方法解决软硬件接口验证问题和完善软硬件架构.H.264解码实验证明多处理器原型功能可行性和物理可实现性.基于该原型的多层次细化方法可有效确保SoC软硬件设计的正确性,并有助于软硬件结构协同设计优化.     

用ADSP—21060芯片构建多处理器DSP系统

采用多处理器数字信号处理（ＤＳＰ）系统是现代数字信号处理技术发展的客观要求,这里介绍了用ＡＤＳＰ—２１０６０芯片作为ＣＰＵ来构建多处理器ＤＳＰ系统的设计实现方案。     

多处理器C6201系统在雷达信号处理中的应用

首先介绍了DSP芯片TNS320C620的特点及一个具有多处理器C6201的通用开发板PENTEK4290。然后从工程和系统的角度出发，设计一个基于该通用开发板的实时雷达信号处理系统，并对该系统中一些关键问题进行了详细的研究。     

媒体多处理器系统芯片中的高效数据搬运机制

媒体处理是一种高宽带流量的数据流处理,系统不仅需要有很强的媒体数据运算能力,还需要高效的数据搬运机制.媒体多处理器系统芯片复杂的内部结构对数据搬运机制的设计提出了新的挑战.根据媒体数据的存储特点,阐述了面向媒体数据搬运、基于任务链表的二维DMA机制;设计了用于媒体多处理器系统芯片的集中式DMA控制器.实验数据表明,在进行MPEG视频解码时,使用二维DMA机制的执行周期比未使用DMA机制的执行周期减少了50 %左右.     

集成电路

8GHz PLL频率合成器；低成本的精密放大器；高灵敏度低功耗的单芯片GPS接收器；可提供千兆位线速吞吐率的GPON ONT系统芯片；支持多处理器和芯片组的主板时钟。     

SoC可重配置处理器平台

随着供应商的功能强劲多处 理器和并行处理器解决方案的不断发布,一个基于平台设计的潮流正在日益高涨。就在最近,几个供应商发布了尚未完全包装的解决方案,其中某些产品还配置了构建有竞争力SoC(系统级芯片）所必需的全部硬件与软件。2000年10月,一家致力于多处理器平台并处于起步阶段的公司Improv Systems推出了首款专用产品-Acappella,一个基于该公司PSA(可编程系统结构)与Jazz处理器结构的VoP(分组语音传输)解决方案。Jazz处理器是一个既可配置又能编程的VLIW(甚长指令字)处理器。Philips是Acappella包的第一位用户。该方…     

PMC-Sierra新推64位MIPSPowered多处理器

PMC-Sierra公司在近日的秋季处理器论坛(Fall Processor Forum)上发布了其第三代高集成64位MIPS-Powered多处理器。这款RM11200处理器采用PMC-Sierra经验证的系统级芯片(SoC)平台设计方案和90纳米CMOS制程工艺，集成两个全新设计的1．8GHz E11K CPU核心，并采用了高速内存和I／O接口，其中包括两个DDR2、两个PCI Express、     

涡轮增压多核系统

相对于传统的单处理器或多处理器芯片，多核架构可提供更高性能、更强运算能力、更高系统密度．同时可降低热量消散。Windows作为通用操作系统，主要用于满足个人用户的家庭需求。因此当满足工业应用的实时性要求时．则需添加Windows控件．Ardence公司的Ardence RTX即可实现对Windows的实时性控制。     

支持多处理器通信的同/异步串口的设计

同/异步串口集成了同步和异步串口的功能,相比于单一功能的串口,配置灵活,且节约芯片资源。通过模块化设计方法实现同/异步串口的设计与仿真,并着重在内部模块设计中体现同步和异步功能的有效结合,合理复用逻辑功能。利用寄存器实现模块同异步功能及参数的可配置性,设计实现了9位唤醒模式,以支持多处理器通信。逻辑综合的结果显示,该串口具有良好的性能。目前,该串口已应用于高端32位DSP,工作稳定。     

基于TDM总线的多处理器系统检测技术的研究

多处理器系统是红外成像探测系统的重要组成部分，随着红外成像探测技术在航天、军事等领域的广泛应用，对系统的可靠性和可维修性提出了更高的要求。为了方便多处理器系统的检测和维修，文章提出了一种基于TDM总线的多处理器系统的检测技术，可以完成电路故障的快速准确定位、系统软件在线修改和信号处理中间结果记录，将系统的检测由系统级上升为芯片级。     

On‐Chip Multiprocessor with Simultaneous Multithreading

As more transistors are integrated onto bigger die, an on‐chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on‐chip multiprocessor, called Raptor, which is composed of four 2‐way superscalar processor cores and one graphic co‐processor. To obtain performance characteristics of Raptor, a program‐driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on‐chip multiprocessor designs.     

基于MC9S08DZ60的CAN总线振动传感器设计

基于单片机MC9S08DZ60和收发器TJA1040,遵循CAN总线协议,设计一款振动传感器。详细介绍整个系统的设计方案及各个模块的硬件电路和软件实现。采集到的数据由CAN总线上传至主控机存储,便于进行分析整理。测试表明,该设备响应快、传输精度高,具有CAN总线实时、可靠、灵活的特点。为生产提供了安全保障。     

CCSim：基于Pin的CMPCache访问模拟器

随着芯片集成制造工艺的日益发展,拥有多级Cache的片上多处理器(CMP)已成为桌面应用和高端计算的主流平台.为了优化程序在CMP下运行性能,文中以Pin工具软件为基础,提出并设计了一个面向CMP体系架构的多级Cache访问模拟器——CCSim.该模拟器不仅可以模拟同构CMP下传统方式的Cache访问,而且还可以对CMP中最后一级共享Cache的竞争访问以及非传统方式的Barcelona式Cache访问模式进行模拟分析.     

多核CPU在HDTV SoC上的实现

以多核CPU在HDTV SoC上的应用为例,简述了HDTV SoC的功能模块划分.探讨了以同核异构方式互连的CPU之间的通信问题,同时还介绍了以此结构为基础的一次完整CPU通信过程.     

The PAPIA system

In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operational.     

The PAPIA system

In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operational.     

VLSI for high-performance graphic control utilizing multiprocessor architecture

This paper describes the VLSI for high-performance graphic control which utilizes two-level multiprocessor architecture. The VLSI chip is constructed of multiprocessor modules processing in parallel, and each processor module is constructed of multiexecutors using pipeline processing. This dedicated VLSI chip, designated as advanced CRT controller (ACRTC), has three processor modules, each independently controlling drawing, display, and timing. The graphic architecture of the drawing processor, which controls graphic drawing, is described. A high-level graphic language based on anX-Ycoordinate system is adopted. High-speed drawing is realized (drawing rate is 500 ns/pixel for drawing a line) by pipeline processing with three executors, the logical address executor, physical address executor, and color data executor.     

Electromigration-induced failure in flip-chip solder joints

The electromigration failure mechanism in flip-chip solder joints through the rapid dissolution of the Cu metallization was studied in detail. The ambient temperature was found to be a very important factor in this failure mechanism. When the ambient temperature was changed from 100°C to 70°C, the time to failure changed from 95 min to 31 days. The results of this study indicate that temperature, as an experimental variable, is not less important than the current density in electromigration study. The surface temperatures of the chip and substrate during electromigration were also measured. The temperature of the Si chip was reasonably homogeneous because of the fact that Si is a very good thermal conductor. It was also reasoned that the high thermal conductivity of the PbSn solder could not support a temperature gradient large enough to induce thermomigration across the solder joint in the present study. Experimentally, no evidence of mass transport caused by thermomigration was observed.     

A class of multiprocessors for real-time image and multidimensionalsignal processing

A 90000-transistor, 50-MIPS (million-instruction-per-second) multiprocessor chip designed for image orthogonal transform is discussed. The architectural principle, derived from a tensorial formalism, is usable for the other linear processings of multidimensional signals (e.g. n-dimensional convolution). A regularity factor of more than 99% was obtained by taking advantage of systolic principles at both chip and bit levels     

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Wireless Personal Communications - The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips...