An analysis of base resistance for alloy junction transistors

For the circular disk type of transistor geometry, as commonly used in alloy junction transistors, base resistance is determined by treating it as a boundary value problem. This treatment results from consideration of the over-all behavior of both minority and majority charge carriers in the base region and leads to an expression for base spreading resistance in terms of alpha, frequency, resistivity, and transistor dimensions. Further consideration of this over-all charge carrier behavior leads to a determination of the entire common-emitter short-circuit input impedance, which in general is complex. Comparison with measurement shows that this impedance, which includes the base resistance, can be calculated accurately over a wide frequency range in terms of physical constants, dimensions, frequency, dc emitter bias, and effective minority carrier lifetime in the base region for small-signal operation of low power alloy junction transistors. Application to other types, such as power transistors and diffused-base transistors, may require extension of the present analysis with a considerable increase in complexity. Limitations and extensions of the analysis in its present form are discussed.     

Minority carrier injection characteristics of the diffused emitter junction

For the double-diffused transistor, a one-dimensional analysis is presented on the minority carrier injection properties of a diffused emitter junction. This junction is bounded on one side by a reverse biased collector and on the other by an ohmic contact of arbitrary recombination velocity. Furthermore, arbitrary magnitudes of minority carrier lifetime are assumed in both the emitter and base regions of this semiconductor device. Injection efficiency characteristics are graphically illustrated throughout a wide range of physical and geometrical parameters. Assuming, for example, variations in the emitter junction depth, injection properties are demonstrated for transistors exhibiting a fixed collector location and also for transistors exhibiting a fixed base width. A comparison is also shown between the calculated minority carrier injection from this analysis and from other, more approximate, methods.     

A physical theory of junction transistors in the collector-voltage-saturation region

A physical theory has been formulated for the operation of junction transistors in the "collector-voltage-saturation" region or "on" region. Transistor characteristics in this region are important for switching applications, Class A or Class B amplifiers, as well as other large signal applications. The formulation is based on the physical consideration that in the "collector-voltage-saturation" region the collector-base junction is forwardly biased, and that the injection level is high. Two-dimensional distributions of carrier densities, current densities, and electric field are obtained for separate portions of the base region. Using these distributions, theoretical expressions are derived for the characteristics of p-n-p and n-p-n transistors including saturation voltage, base input voltage, and dc current amplification factor. Good agreement between theoretical and experimental results indicates that the approximations used in the theory are valid. Numerical calculations have been carried out for the saturation voltage, base input voltage, and dc current amplification factor for different geometrics and material properties. The calculation illustrates the use of the theory for quantitative designs of transistor characteristics.     

Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.     

Analysis of the early voltage in bipolar transistors

The Early voltage of the bipolar transistor is calculated considering the current gain of the device due to the emitter injection efficiency as well as the volumetric recombination in the base. The impurity profile in the base is assumed to be exponential. The calculated values and the measured values of the Early voltage VAare seen to be in good agreement. Seven high-voltage transistors having a wide range of physical and device parameters were taken for the experimental verification. The Early voltage is seen to increase with the increase in the diffusion length of minority carriers in the base where as it decreases when the emitter Gummel number rises. Curves are also plotted showing the effect of other parameters on VA. The values of VAare also calculated when the minority-carrier lifetime in the base is infinite and these values are compared with the corresponding measured values. As a check on the analysis, comparison is made between the calculated and the measured values of the Early voltage of the devices in the inverse mode of operation. The agreement is good.     

Intermodulation distortion of a bipolar common-emitter amplifier with arbitrary emitter impedance and input matching network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.     

Modeling and characterization of SIPOS emitter and quasi-SISemitter bipolar transistors

SIPOS (semi-insulating polycrystalline Si) emitter bipolar transistors have been fabricated with a common-emitter current gain of 8000 and a figure of merit (gain divided by intrinsic base sheet resistance) of 200 (kΩ/sq)^-1. The high gain is attributed to a relatively low interface recombination velocity of the emitter contact, as measured by photo-induced microwave reflectometry. The cutoff frequency is measured to be 250 MHz, the low value attributed to a large emitter contact resistance of the SIPOS emitter. The authors suggest that a new figure of merit-transconductance divided by emitter resistance-should be considered for the comparison of the high-frequency performances of high emitter efficiency bipolar transistors. A quasi-SIS semiconductor-insulator-semiconductor emitter bipolar with a poly-Si emitter and undoped SIPOS as an interfacial layer was also fabricated. By incorporating a field-enhancement factor in the SIPOS, the behavior of this transistor is successfully explained by a SIS emitter model. The ideality factor ratio in the Gummel plot is attributed to the different barrier heights of electrons and holes at the SiO₂/n-Si interface     

Large signal turn-on response of the junction transistors including nonlinear effects

The large-signal transient behavior of transistors must be considered as nonlinear phenomena. In this paper, the nonlinearity of the transient behavior of transistors in the active region are considered, and the charge control method is extended to include this nonlinearity. Using a one-dimensional homogeneous-base transistor model, the current variation of small-signal time constants in the charge control concept are analyzed in terms of emitter efficiency, surface recombination, and generated field in the base region. From the results of the small signal analysis, the large-signal time constants have been defined as a function of injection ratio. From the charge control equation founded on the large-signal time constants, the rise time is calculated including the current variations of time constants and voltage variation of junction capacitance. The results of the analysis are also verified by experimental measurements.     

On the theory of DC amplification factor of junction transistors

According to Webster's phenomenological theory, the base current consists of three terms arising from 1) surface recombination 2) bulk recombination, and 3) non-unity emitter efficiency. In this paper, the diffusion equation inside the base region of an alloyed transistor is solved, and an analytic expression for the dc amplification factor is presented in terms of arbitrary bulk lifetime and surface-recombination velocity and the geometry of the transistor. The surface-recombination term depends on the distribution of the injected carriers along the emitter-base boundary, and hence, it increases as the emitter current increases on account of the base-resistance bias effect which tends to concentrate the minority carriers near the periphery of the emitter. The falloff in beta at high-emitter current is attributed mainly to an increase in the surface-recombination term, contrary to Webster's theory. A comparison with Webster's theory is made on units having the same bulk property but different surface treatments. Experimental results give strong support to the present theory.     

On the recombination currents effect of heterostructure-emitter bipolar transistors (HEBTs)

In this paper, we will demonstrate the effect of recombination current on the electrical properties of heterostructure-emitter bipolar transistors (HEBTs). For comparison, an AlGaAs/GaAs and an AlInAs/GaInAs HEBT are fabricated with the same layer structure. The theoretical analysis shows that the neutral-emitter recombination current in the neutral emitter regime is a significant factor for determining transistor characteristics. For the AlGaAs/GaAs HEBT, the hole diffusion length is larger than the emitter thickness, so that most of holes can be reflected back at the confinement layer due to the hole recombination current being low in the neuter-emitter region. Thus, the high emitter injection efficiency and current gain can be achieved simultaneously. On the other hand, for the AlInAs/GaInAs HEBT, the increase of recombination current at neutral emitter regime and the existence of potential spike could reduce the emitter injection efficiency at large V_BE voltage. Hence, the non-1KT component of collector current is enhanced and the characteristics of transistor are degraded. However, a lower offset voltage of 40 mV is obtained attributed to the low base surface recombination current for the AlInAs/GaInAs HEBT. All of these experimental results are consistent with the theoretical analysis.     

Calculation of surface recombination current in bipolar microelectronic structures subjected to ionizing radiation

The surface recombination current of bipolar transistors is calculated as a function of the charge of surface states, which is determined by the position of Fermi quasi-levels under a direct bias voltage across the emitter junction. It is shown that the calculation of radiation-induced surface recombination current can be reduces to the solution of the Shockley equation at the interface between a passivating oxide and the base taking into account the effect of surface states in the passivating oxide on the charge carrier concentration. A rigorous expression is derived for the surface recombination current per unit length.     

The tetrode power transistor

Power transistor circuits are characterized by the fact that the collector current must swing over a wide range of values during any complete cycle of operation. One disadvantage of present-day alloyed junction power transistors is that the current gain decreases with increasing collector current. This causes distortion in linear applications and makes temperature stabilization in switching circuits more difficult. Power transistors having emitter areas large enough to handle currents in the amperes range can be made as tetrodes by use of an annular ring geometry. Experimental results show that the gain characteristics can be altered by applying a bias voltage or a portion of the signal voltage transversely across the base. The gain characteristic can be made flatter for improved fidelity in audio applications, or even reversed to give increasing gain with collector current for certain switching applications. Practical circuitry utilizing the improved gain characteristics of power tetrodes has been developed, and the annular geometry permits the fabrication of tetrodes using conventional alloying techniques.     

Physical mechanisms leading to deterioration of transistor life

Life tests on surface-barrier-type transistors have been conducted at various temperatures and power levels to identify and characterize the mechanisms which cause the transistor characteristics to deteriorate with time. Three mechanisms have been isolated: the formation of solution cavities in the base of the transistor, an increase in surface recombination velocity, and a decrease in surface resistance. In the normal surface-barrier transistor, the formation of solution cavities proceeds with an activation energy of about 20,000 cal. mole. This leads to an exponential dependence of life expectancy on temperature and dissipation. The formation of solution cavities is eliminated by the microalloy process, in which case the life expectancy is probably determined by the decrease in surface resistance or the increase in surface recombination velocity. The increase in surface recombination velocity causes a well-correlated decrease in current gain and grounded-base output impedance. The decrease in surface resistance produces an increase in the collector "saturation" current and may contribute to a decrease in output resistance. The formation of solution cavities brings about a decrease in punch-through voltage and grounded-emitter output impedance.     

Calculation of the breakdown characteristics of bipolar transistors using a two-dimensional model

The location of avalanche-breakdown in the common emitter output characteristics of bipolar transistors has been calculated for a circular emitter geometry. A two-dimensional model takes account of the very important voltage drop across the base spreading resistance. The dependence of the breakdown points on the bias voltage and the series resistance at the base terminal can be described by simple formulas, which agree quite well with experimental results.     

Bipolar Microwave Linear Power Transistor Design

Design considerations for n-p-n bipolar microwave linear power transistors are discussed. Optimization procedures are presented for determining emitter width for a specfic operation frequency, emitter ballasting resistance, and active area geometry based on calculated temperature distributions. A transistor chip designed for 4-GHz operations using these procedures achieved a linear power output of 27.5 dBm at a 1-dB compressed gain of 7 dB with a power added efficiency of 23 percent. Junction temperature rise was limited to 90/spl deg/C.     

Collector recombination lifetime from the quasi-saturation analysisof high-voltage bipolar transistors

A novel method of measuring the collector recombination lifetime, which is independent of emitter effects, is presented by extending the quasi-saturation analysis of high-voltage bipolar transistors to the high-current-density regime. The technique is supported by theory, and experimental results are presented on transistors fabricated with different emitter properties. This is a nondestructive method and gives the lifetime values at the current densities normally encountered when the transistor is in actual operation. The values for the collector recombination lifetime obtained by the present method are independent of the properties of the emitter region     

Measurement of the low-current base and emitter resistances of bipolar transistors

A new ac method is proposed to measure the emitter and base resistances of bipolar transistorsat low current levels at which the effective transistor geometry is given by the processing and is unaffected by the changes induced by high currents. The technique is based on a measurement of the input impedance at frequencies below about 50 MHz. It is particularly suited for the measurement of the physical emitter resistance of scaled transistors. The method is illustrated on microwave transistors with metal contacts and on self-aligned digital transistors with polysilicon contacts. A comparison of the results obtained using this method with those from dc methods operating at high currents can be used to explore the current dependencies of the resistances. The technique is applicable both for homojunction and heterojunction transistors.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

High-level transistor operation and transport capacitance

A two-dimensional analysis of high-level transistor operation is presented which includes the effects of an extended base region, internal emitter biasing, γ-falloff, unequal collector and emitter dimensions, and surface recombination. The transistor model considered is directly appropriate to the strip-type geometry, but also yields results which are approximately valid for the ring-and dot-type structures under certain conditions. Transforming the geometry permits a solution to be obtained for the charge-density distribution in the base as well as the current density distribution at the emitter and collector junctions. From these relations, both the collector and emitter transport (diffusion) capacitances are also determined. Two complete numerical evaluations of the theoretical results are given, first for a symmetrical unit with equal emitter and collector dimensions, and second for an unsymmetrical unit with the collector dimension 24 per cent greater than that of the emitter. It is indicated that an appreciable fraction of the total base charge can exist external to the emitter and collector, particularly for very high-level operation, causing large increases (1.5 to 3 times the one-dimensional values) in both the emitter and collector transport capacitances, particularly for units having grossly extended base regions and low surface-recombination velocities. Further shown is the effect of increasing the collector dimension over that of the emitter; the capacitances are appreciably lowered and the transport efficiency (and thus the current gains) is increased. Finally, some collector transport capacitance measurements are presented covering the entire operating range which tend to substantiate the theoretical results.     

High-current-gain submicrometer InGaAs/InP heterostructure bipolartransistors

Common-emitter current gains of 115 and 170 are achieved in transistors with emitter dimensions as small as 0.3×3 and 0.8×3 μm², respectively. These results are comparable with scaling experiments reported for Si bipolar devices and represent a significant improvement over AlGaAs/GaAs heterostructure bipolar transistors. Both the low surface recombination velocity and nonequilibrium carrier transport in the thin (800-Å) InGaAs base enhance the DC performance of these transistors