Determination of physical parameters of diffusion and drift transistors

The dynamic properties of drift and diffussion transistors are studied under both low- and high-level injection conditions in terms of the excess carrier charge in the base region. Subject to the assumptions of effectively one-dimensional device geometry with exponential impurity grading and collector conductivity much greater than that of the base, methods of determination of the main physical and high-frequency equivalent-circuit parameters of transistors are presented, utilizing the bias dependence of excess carrier charge in the base and space charge in the collector-depletion region. It is shown that measurement of the base transit time and the junction capacitances under low-level injection conditions enables the following physical parameters to be determined: base field parameterm = DeltaV/(kT/q), base width, base impurity distribution, emitter area, collector-depletion layer width. All the measurements are carried out at relatively low frequencies. Solutions for the base charge distribution, and hence charge-defined transit time, have been derived for the cases of exponential and erfc impurity grading under high-level injection conditions, assuming one-dimensional device geometry, constant base cross-sectional area, andDandmicroindependent of injection level. Experimental results have been found to differ greatly from the theoretical expectations based on these assumptions, the drift transistor showing greater and the diffusion transistor less than the predicted dependence on injection level. Explanations for the observed effects have been put forward in terms of reduction of emitter area and ofDandmicroat high injection levels.     

收集区制在半绝缘磷化铟衬底中的InGaAsP/InP异质结双极晶体管

本文提出并成功地试制了一种InP异质结双极型晶体管.其主要特点是利用在半绝缘InP衬底中注硅形成收集区,然后再进行液相外延形成基区和发射区.本结构能有效减少基区一收集区的结电容C_(BC)和寄生电容.避免了薄基区上制作基极欧姆接触时经常发生的基极-收集极之间的短路问题,提高了器件的可靠性结果表明,该器件具有较高的共发射极电流增益(h_(FE)=150～250),并能够双向工作.文章对该结构的优点进行了分析,给出了器件的工艺过程.     

Submicrometer fully self-aligned AlGaAs/GaAs Heterojunction bipolar transistor

A novel submicrometer fully self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) for reducing parasitic capacitances and resistances is proposed. The fabrication process utilizes SiO2sidewalls for defining base electrode width and separating this electrode from both emitter and collector electrodes. Measured common-emitter current gain β for a fabricated HBT with 0.6 × 10-µm²emitter dimension and 0.7 × 10-µm²× 2 base dimension is 26 at 9 × 10⁴-A/cm²collector current density.     

Fully Radiative Current Path Structure (FRACS) for sub-0.1 μmemitter transistor

A new structure is proposed for bipolar transistors - FRACS (Fully Radiative Current Path Structure). A FRACS transistor has a line emitter and a cylindrical base and collector or a point emitter and a spherical base and collector. Device parameters of the FRACS transistor is obtained by extending the conventional one-dimensional transistor model to a two- or three-dimensional model. In this structure, base transit time is reduced as the emitter size is reduced by radiative collector current flow. Using this model, a general bipolar transistor with a shallow link base is found to increase the cutoff frequency as the emitter size is reduced. The Kirk effect is suppressed in this structure because of the small collector current density at the collector-base junction. The effect was experimentally examined. A cylindrical base was fabricated by thermal diffusion of boron to achieve the FRACS transistor. Cutoff frequency was observed to increase as the emitter size was reduced. Maximum cut-off frequency of 64 GHz was achieved by this transistor with a 25-nm thick base formed by rapid vapor-phase diffusion     

All-organic vertical transistor in an analogous n-semiconductor/metal/p-semiconductor trilayer structure

We report on the development and characterization of an all-organic vertical transistor, consisting of a p-type conjugated polymer, poly(bithiophene), as collector material, a poly(ethylene dioxythiophene)/poly(styrene sulfonate) layer as base material and a n-type molecule layer, Alq₃, as emitter material. The transistor is operated under direct bias in the common-emitter mode, being its operation based upon charge recombination of the injected majority carriers at the emitter–base interface. Experimental results have yielded current amplification factors up to 7. We also demonstrate that tunneling controls the transport characteristics of the device.     

A theory and some characterisitcs of power transistors at high-level conditions

The concentration of injected carriers is large compared with the impurity doping concentration in the base region of a power transistor operating at high level. Carrier concentration and characteristics of a two-dimensional transistor model are calculated for this case. Emitter and base contacts are in the form of strips. Most of the injected emitter current reaches the collector while the remainder recombines in the slightly doped base region under the emitter, resulting in a current in the highly doped base contact. In addition, a recombination current generated in the base region under the base contact is added to this base current and results in a decrease of current gain. In order to analyze the base recombination current, a special transistor with divided collector contacts was prepared. In this way, the collector current due to the region under the emitter contact can be separated from the collector current due to the region under the base contact. The presented theory could be verified. Additional corrections are necessary, however, in the direction of the current in the slightly doped base region.     

Base transport factor calculations for transistors with complementary error function and Gaussian base doping profiles

By taking account of the carrier mobility degradation at high impurity concentrations, the high-frequency base transport factor of an n-p-n germanium base transistor was computed numerically for different base doping levels. The doping profiles under consideration were Gaussian and complementary error functions. The base doping level adjacent to the emitter was optimized for minimum base transit time. The optimum values are 4×10¹⁷atom/ cm³for complementary error function profile and 2×10¹⁷atom/cm³for Gaussian profile. The effects of emitter barrier capacitance, base resistance, collector barrier capacitance, and the collector depletion layer on the overall frequency response of a junction transistor are also discussed.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Characterization and measurement of the base and emitter resistances of bipolar transistors

Most previously published methods of measuring transistor base resistance are surveyed and compared. The input impedance circle diagram method is examined in detail and correction factors due to parasitic capacitances are derived. Emitter series resistance is also estimated from this data. A new method of measuring base resistance requiring much less measurement effort is introduced and shown to give good agreement with the circle diagram method. This method is called the phase cancellation method and gives an estimate of base resistance from the common base input impedance at the collector current where its imaginary part is zero. Also an estimate of series emitter resistance is obtained from this measurement and shown to agree well with other methods.     

The tetrode power transistor

Power transistor circuits are characterized by the fact that the collector current must swing over a wide range of values during any complete cycle of operation. One disadvantage of present-day alloyed junction power transistors is that the current gain decreases with increasing collector current. This causes distortion in linear applications and makes temperature stabilization in switching circuits more difficult. Power transistors having emitter areas large enough to handle currents in the amperes range can be made as tetrodes by use of an annular ring geometry. Experimental results show that the gain characteristics can be altered by applying a bias voltage or a portion of the signal voltage transversely across the base. The gain characteristic can be made flatter for improved fidelity in audio applications, or even reversed to give increasing gain with collector current for certain switching applications. Practical circuitry utilizing the improved gain characteristics of power tetrodes has been developed, and the annular geometry permits the fabrication of tetrodes using conventional alloying techniques.     

GaAs---GaAlAs heterojunction transistor for high frequency operation

A bipolar transistor structure is proposed having application for either high frequency operation or integration with certain types of light emitting devices. The structure involves liquid phase epitaxially grown layers of GaAs for the collector and base regions, and of Ga_1−xAl_xAs for the heterojunction emitter. The high frequency potential of this device results primarily from the high electron mobility in GaAs and the ability to heavily dope the base region with slowly diffusing acceptors. The Ga_1−xAl_xAs emitter region provides a favorable injection efficiency and, because it is etched preferentially relative to GaAs, access to the base layer for making contact. Transistor action with d.c. common emitter current gains of 25 have been thus for observed. Calculations of the high speed capability of this transistor are presented.     

Submicron scaling of HBTs

The variation of heterojunction bipolar transistor (HBT) bandwidth with scaling is reviewed. High bandwidths are obtained by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. Narrow collector junctions can be obtained by using substrate transfer or collector-undercut processes or, if contact resistivity is greatly reduced, by reducing the width of the base ohmic contacts in a mesa structure. HBTs with submicron collector junctions exhibit extremely high f_max and high gains in mm-wave ICs. Transferred-substrate HBTs have obtained 21 dB unilateral power gain at 100 GHz. If extrapolated at -20 dB/decade, the power gain cutoff frequency f_max is 1.1 THz. f_max will be less than 1 THz if unmodeled electron transport physics produce a >20 dB/decade variation in power gain at frequencies above 110 GHz. Transferred-substrate HBTs have obtained 295 GHz f_T. The substrate transfer process provides microstrip interconnects on a low-ϵ_r polymer dielectric with a electroplated gold ground plane. Important wiring parasitics, including wiring capacitance, and ground via inductance are substantially reduced. Demonstrated ICs include lumped and distributed amplifiers with bandwidths to 85 GHz and per-stage gain-bandwidth products over 400 GHz, and master-slave latches operating at 75 GHz     

Leakage current mechanisms in SiGe HBTs fabricated using selectiveand nonselective epitaxy

SiGe heterojunction bipolar transistors (HBTs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p⁺ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor. In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe extrinsic base. In these transistors, the Gummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through of the base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakage is shown to be due to a Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole-Frenkel and band to band tunneling. These results are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter     

A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits

A physics-based scalable transistor model is described which allows accurate consideration of avalanche-breakdown effects in bipolar circuit simulation. The three-dimensional model consists of six lumped transistor elements, which are connected via elements of the base and emitter-contact resistance. Analytical relations are given to calculate the elements of this six-transistor model (6TM) for arbitrary emitter dimensions from measured area- and length-specific transistor parameters. As a core of the transistor elements, all kinds of conventional transistor models can be used provided an adequate avalanche current source is implemented between the internal collector and base nodes. The validity of this 6TM has been verified under dc and fast transient conditions by simulations and measurements.     

选择离子注入集电极技术研究

为提高超高速双极晶体管的电流增益 ,降低大电流下基区扩展效应对器件的影响 ,将选择离子注入集电区技术 (SIC)应用于双层多晶硅发射极晶体管中。扩展电阻的测试结果显示出注入的 P离子基本上集中在集电区的位置 ,对发射区和基区未造成显著影响。电学特性测量结果表明 ,经过离子注入的多晶硅发射极晶体管的电流增益和最大电流增益对应的集电极电流明显高于未经离子注入的晶体管。因此 ,在双层多晶硅晶体管中采用 SIC技术 ,有效地降低了基区的扩展效应 ,提高了器件的电学特性。     

Proposal and demonstration of multi-emitter HBTs

The authors have designed and tested InGaAs-InAlGaAs multi-emitter HBTs (ME-HBTs). The emitter electrodes of the transistor work as both an emitter and a base depending on their potential. A highly doped emitter layer was used for a low turn-on voltage for the collector current. Using an ME-HBT, the room-temperature operation of AND/NOR gates was tested     

An analysis of base resistance for alloy junction transistors

For the circular disk type of transistor geometry, as commonly used in alloy junction transistors, base resistance is determined by treating it as a boundary value problem. This treatment results from consideration of the over-all behavior of both minority and majority charge carriers in the base region and leads to an expression for base spreading resistance in terms of alpha, frequency, resistivity, and transistor dimensions. Further consideration of this over-all charge carrier behavior leads to a determination of the entire common-emitter short-circuit input impedance, which in general is complex. Comparison with measurement shows that this impedance, which includes the base resistance, can be calculated accurately over a wide frequency range in terms of physical constants, dimensions, frequency, dc emitter bias, and effective minority carrier lifetime in the base region for small-signal operation of low power alloy junction transistors. Application to other types, such as power transistors and diffused-base transistors, may require extension of the present analysis with a considerable increase in complexity. Limitations and extensions of the analysis in its present form are discussed.     

InGaAsSb/InP Double Heterojunction Bipolar Transistors Grown by Solid-Source Molecular Beam Epitaxy

This letter investigates the dc characteristics of a double heterojunction bipolar transistor (DHBT) with a compressively strained InGaAsSb base, which is grown by solid-source molecular beam epitaxy. The novel InP/InGaAsSb HBT has a lower base/emitter (B/E) junction turn-on voltage, a lower offset voltage, and a junction ideality factor closer to unity than the conventional InP/InGaAs composite collector DHBT. These characteristics are attributed to the transistor's type-I B/E junction and type-II base/collector junction, which facilitates carrier transport for low power, high current density, and high-speed operation. Heterojunction bipolar transistors (HBTs), InP/InGaAsSb, molecular beam epitaxy (MBE).     

Monte Carlo analysis of nonequilibrium electron transport inInAlGaAs/InGaAs HBT's

A Monte Carlo analysis of nonequilibrium electron transport in InAlGaAs/InGaAs HBTs is discussed. The discussion focuses on hot electron transport in a heavily doped p-type base from the viewpoint of high-speed transistor performance. Simulation shows that a hybrid base structure which incorporates an abrupt emitter/base junction and a graded base layer has a shorter base transit time than conventional uniform base structures with an abrupt emitter or fully graded base structures. The short base transit time is due to the high initial electron velocity provided by the abrupt emitter/base junction and the acceleration of energy-relaxed electrons (which cause a lowering of average electron velocity in the base region) by a built-in electric field in the graded base layer. The influence of hot electron injection into the collector is also considered     

On the transient response of emitter followers

Transient response of emitter followers is analyzed incorporating the effects of collector-base and load capacitances, gain-bandwidth product, excess delay, and base, collector, and load resistances. Basic considerations pertaining to transient response and instabilities are discussed, and numerical results are given for a wide range of circuit parameters.