数字扫描探针显微镜中的DSP技术

本文介绍了我们研制数字ＳＰＭ仪器时在ＤＳＰ芯片选型、ＳＰＭ－ＤＳＰ插卡设计、开发工具ＤＳＰ软件及其基本算法方面的考虑和解决方案并简介一种采用德州仪器公司ＴＭＳ３２０Ｃ５０ＤＳＰ芯片设计的ＳＰＭ仪器该仪器已实现ＳＴＭ模式、接触ＡＦＭ模式、非接触ＡＦＭ模式,并具有和多种ＳＯＰＭ头部接口的开放性结构。     

硬件控制的8k×8 SRAM/EEPROM U630H64原理及接口应用

Ｕ６３０Ｈ６４内含反相映射的８ｋ字节ＳＲＡＭ和８ｋ字节ＥＥＰＲＯＭ，通过命令可以将ＳＲＡＭ中的数据写入ＥＥＰＲＯＭ或把ＥＥＰＲＯＭ中的数据回送至ＳＲＡＭ，以备断电时的数据保护。该芯片所采用保护数据的方法是除ＮＶＳＲＡＭ、Ｆｌａｓｈ之外的一种独特的方法。本文介绍了该芯片的内部结构，并给出了与单片机的接口电路。     

世界最高速16M SRAM

世界最高速１６ＭＳＲＡＭ据日本《电子材料》杂志１９９３年第４期报道，日本索尼公司已研制成世界最高存取速度９ｕｓ的１６ＭｂＳＲＡＭ。这种ＳＲＡＭ在电路内进行信号放大的读出放大器中，采用了输入阻抗小的反馈式电流读出放大器，并可用作高速存取。以前的ＳＲＡＭ...     

CMOS SRAM存储单元研究

阐述了采用１．０μｍ ＣＭＯＳ技术制作的２５６ｋ ＳＲＡＭ的存储单元。论述了存储单元的性能在ＣＭＯＳ ＳＲＡＭ中的重要性，分析了存储单元的工作原理，结构和主要参数性能。文章对几种类别的ＣＯＭＳ ＳＲＡＭ存储单元进行了分析比较，推测了技术发展趋势。     

一种新型Rail-to-Rail运算放大器的设计与分析

提出了一种采用线性跨导输入级的Ｒａｉｌ－ｔｏ－Ｒａｉｌ运算放大器,输入级的跨导基本实现了与共模输入 电压无关,而只与工艺参数和工作电压有关。采用了复合晶体管的设计,使管ＮＭＯＳ和等效ＰＭＯＳ的电学参数一致,摈弃了由于ＰＭＯＳ及ＮＭＯＳ的不一致性而采取的补偿措施。输出级采用甲乙类ＣＭＯＳ结构,实现了输出的Ｒａｉｌ－ｔｏ－Ｒａｉｌ。     

SONY DSR—30P DVCAM录像机

１　磁带本录像机使用标准ＤＶＣＡＭ或Ｍｉｎｉ－ＤＶＣＡＭ磁带。２　菜单设置·按ＭＥＮＵ（菜单）键,再按ＣＵＲＳＯＲ（光标）的↑／↓键,选定ＳＥＴＵＰＭＥＮＵ（菜单设置）后,按ＥＸ－ＥＣＵＴＥ（执行）键,进入菜单设置：（１）Ｌ１ＩＮＶＩＤＥＯ（１路输入视频）·Ｓ当Ｓ端和复合端都接有信号时,若要选择Ｓ视频信号,则设置到Ｓ的位置。若只有复合端接有信号,则自动选择复合视频。·ＮＯＲＭ当Ｓ端和复合端都接有信号时,若要用复合视频信号,则选择ＮＯＲＭ项。（２）ＡＵＤＩＯＭＯＤＥ（音频模式）·１６当设置到１６时…     

ORACLE数据库性能优化

ＯＲＡＣＬＥＲＤＢＭＳ已在各行业得到了广泛的应用和关注。本文对ＯＲＡＣＬＥＲＤＢＭＳＶ６．０的运行机制进行了分析，并对数据库规范化设计、数据参数调整、ＳＱＬ优化等优化系统的方法进行了讨论。     

COMPACT STAR信函分拣机及SATRUN网络邮件处理系统

ＣＯＭＰＡＣＴＳＴＡＲ信函分拣机及ＳＡＴＲＵＮ网络邮件处理系统卡特一、ＣＯＭＰＡＣＴＳＴＡＲ信函分拣机ＣＯＭＰＡＣＴＳＴＡＲ分拣机采用标准组件的模块化概念，光纤传输及先进的信函跟踪与控制技术，分拣速度达每小时３．８万封信件。产品质量符合ＩＳＯ９００１...     

MSCDEX的使用

ＭＳＣＤＥＸ的使用邵振付计算机对ＣＤ－ＲＯＭ驱动器的识别与操作同ＣＤ－ＲＯＭ驱动器的配置有关，这就是ＭＳＣＤＥＸ和ＣＤ－ＲＯＭ驱动程序的共同任务，下面作一简单介绍。ＭＳＣＤＥＸ命令提供ＣＤ－ＲＯＭ驱动器的配置、安装功能，可通过ＡＵＴＯＥＸＥＣ．ＢＡＴ...     

MC68HC05SR3芯片介绍

ＭＣ６８ＨＣ０５ＳＲ３芯片介绍黄小平一、基本结构及特征ＭＣ６８ＨＣ０５ＳＲ３ＨＯＭＯＳ微控制器是低功耗单片微控制器Ｍ６８ＨＣ０５家族的一员。这个Ｓ位的微控制器单元（ＭＣＵ）包含有在片振荡器，ＣＵＰ、ＲＡＭＥＯＭ、Ｉ／Ｏ，定时器及Ａ／Ｄ。ＭＣ６８ＨＣ０...     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

高速低功耗SRAM中灵敏放大器的设计

本文对比分析了运放型、交叉耦合型和锁存器型灵敏放大器三种不同的SRAM灵敏放大器的基本结构并通过仿真比较了它们的优缺点,在此基础上设计了读出放大时间在最坏情况下需0.5 ns,静态维持功耗约为0.1 mW的SRAM灵敏放大器.     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

A 4-Mb (512 K words by 8-b) CMOS static RAM (SRAM) with a PMOS thin-film transistor (TFT) has been developed. The RAM can obtain a much larger data-retention margin than a conventional high-resistive load-type well by using the PMOS TFT as a memory cell load. An internal voltage down-converter architecture with an external supply voltage-level sensor not only realizes a highly reliable 0.5-μm MOS transistor operation but also a sufficiently low standby-power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a 0.5 μm, triple-poly, and double-aluminum with dual gate-oxide-thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively     

Impact and mitigation of SRAM read path aging

This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement).     

一种应用于DSP嵌入式存储器的灵敏放大器设计

提出了一种新型灵敏放大器,电路由单位增益电流传输器、电荷转移放大器及锁存器三部分组成。基于0.18μm标准CMOS单元库的仿真结果表明,与现有几种灵敏放大器相比,新型灵敏放大器具有更低的延时和功耗,在1.8 V工作电压、500 MHz工作频率、80μA输入差动电流以及DSP嵌入式SRAM6T存储单元测试结构下,每个读周期的延迟为728 ps,功耗为10.5fJ。与电压灵敏放大器相比,延迟减少约41%,功耗降低约50%;与常规电荷转移灵敏放大器相比,延迟减少约22%,功耗降低约37%;与WTA电流灵敏放大器相比,延迟减少11%,功耗降低31.8%。     

A current-controlled latch sense amplifier and a staticpower-saving input buffer for low-power architecture

Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM     

A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design

A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt–Trigger-based dual-$V _{rm HL}$ APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%–87% over the traditional current-mirror sense amplifier is achievable.      

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

一种新型的SOI灵敏放大器

本文利用"灵巧的体接触(Smart-Body-Contact)"技术设计出一种新型的SOI灵敏放大器.采用Hspice软件对体硅的和新型的交叉耦合灵敏放大器进行模拟和比较,发现新型的交叉耦合灵敏放大器比体硅的交叉耦合灵敏放大器延迟时间缩短30%,最小电压分辨可达0.05V.最后,我们成功地将该电路应用于CMOS/SOI 64Kb SRAM电路,电路存取时间仅40ns.