突发性业务环境下周期性信元流通过ATM复接器的时延抖动

在输入ＡＴＭ网络的业务源中，周期性元流是很重要的一种，本文精确地分析了一个有限缓存在的ＡＴＭ复接器，其输入业务源由一路周期性信元流，多路随机性贝努利（Ｂｅｒｎｏｕｌｌｉ）信元流和突发性两状马尔科夫调制贝努利（ＭＭＢＰ）信元泫构成，得出了该路周期性信元流的排队时延分布，时延抖动的自相关函数和功率谱，揭示了突发性业务环境下周期性信元流通过ＡＴＭ复接器的时延抖动行为，计算机模拟验证了分析结果的正确性。     

具有质量控制功能的ATM交换节点的性能分析

本文提出一种用于ＡＴＭ网的质量控制方法－动态到达控制（ＤＡＣ），分析了采用ＤＡＣ的ＡＴＭ交换节点中，各类业务信元的丢失概率和平均时延，分析结果表明，ＤＡＣ是一种有效的质量控制方式，它能够提供多种服务等级以满足不同的需要，减小所有信元的平均时延，提高系统的有效吞吐量。     

突发性业务环境下周期性信元流通过ATM复接器的时延抖动

在输入ATM网络的业务源中,周期性信元流是很重要的一种.本文精确地分析了一个有限缓存的ATM复接器,其输入业务源由一路周期性信元流、多路随机性贝努利(Bernoulli)信元流和突发性两状态马尔科夫调制贝努利(MMBP)信元流构成.得出了该路周期性信元流的排队时延分布、时延抖动的自相关函数和功率谱.揭示了突发性业务环境下周期性信元流通过ATM复接器的时延抖动行为.计算机模拟验证了分析结果的正确性.     

话音ATM交换——一种现现的网络过渡方案

首先介绍了几种基于ＡＴＭ的语音交换方案，重点提出一种６４ｋｂ／ｓ的话音ＡＴＭ的实现模型。该系统包含了ＳＴＭ交换与ＡＴＭ交换间的相互转换，并能有效地解决诸如信元打包时延，信元时延抖动，以及系统带宽利用率等关键环节，最后还介绍了有关话音ＡＴＭ交换交换技术的其它热点。     

ATM网内有信元时延变化

文章介绍了ＡＴＭ网内信元时延变化（ＣＤＶ）的基本定义及其相关的一些概念，着重分析服信元时延变化对于流量控制和业务终端的影响，并从一个固定速率的连接出发给出了两种定义的ＣＤＶ分布的仿真结果，发加深对基本概念的理解。     

ATM网络中恒定比特率和可变比特率语音通信

分析了ＡＴＭ（异步转移模式）网络中恒定比特率（ＣＢＲ）和可变比特率（ＶＢＲ）语音通信方式，讨论了ＩＴＵ－Ｔ１９９７年新颁布的ＡＴＭ可变比特率业务适配标准ＡＡＬ２，给出了信元装配实例。针对ＶＢＲ业务相对ＣＢＲ业务有较大不同的网络传输时延特性，着重分析了语音信号作为ＶＢＲ业务采用ＡＡＬ２适配标准时，通过ＡＴＭ网络传输时的装配时延问题。     

话音ATM交换——一种现实的网络过渡方案

首先介绍了几种基于ＡＴＭ的话音交换方案，重点提出一种６４ｋｂｓ的话音ＡＴＭ交换（ＶＯＡ）的实现模型．该系统包含了传统ＳＴＭ交换与ＡＴＭ交换间的相互转换，并能有效地解决诸如信元打包时延、信元时延抖动，以及系统带宽利用率等关键环节．最后还介绍了有关话音ＡＴＭ交换（ＶＯＡ）技术的其它热点     

ATM技术

ＡＴＭ是异步传送模式的简称 ,即在ＡＴＭ传输模式中 ,信息被分成信元来传递 ,而包含同一用户信息的信元不需要在传输链路上周期性出现 ,所以这种传输模式是异步的。ＩＴＵ -Ｔ定义ＡＴＭ为“以信元为信息传输、复接和交换的基本单位的传送方式”。所谓的传送是指电信网中传输、复接和交换方式的整体。ＡＴＭ协议包括物理层、ＡＴＭ层、ＡＴＭ适配层和高层。适配层采用了ＡＡＬ１、ＡＡＬ２、ＡＡＬ３／４和ＡＡＬ５等多种协议来支持不同的用户业务。根据源和目的地之间的定时关系、比特率特性以及连接方式 ,ＡＴＭ适配层的业务可划分为Ａ、…     

基于输入缓存机制的ATM网络优先级流控策略

提出一种基于输入缓存机制的ＡＴＭ网络优先级流控策略，并运用系统仿真技术对采用该优先级流控及ＦＩＦＯ输入流控两种方案的ＡＴＭ多媒体网络性能进行计算机仿真研究。结果表明：采用优先级流控策略将改善ＡＴＭ多媒体网非实时信元丢失率及实时信元排队时延性能，具有较大实用价值。     

基于输入缓存机制的ATM网络优先级流控策略

提出一种基于输入缓存机制的ＡＴＭ网络优先级流控策略，并运用系统仿真技术对采用该优先级流控及ＦＩＦＯ输入流控两种方案的ＡＴＭ多媒体网络性能进行计算机仿真研究。结果表明：采用优先级流控策略将改善ＡＴＭ多媒体网非实时信元丢失率及实时信元排队时延性能，具有较大实用价值。     

DELAY JITTER OF A PERIODIC CELL STREAM THROUGH AN ATM MULTIPLEXER IN A BURSTY TRAFFIC ENVIRONMENT

The periodic cell stream is a very important member among the input traffic sources in ATM networks. In this paper, a finite-buffered ATM multiplexer with traffic sources composed of a periodic cell stream, multiple i.i.d Bernoulli cell streams and bursty two-state Markov Modulated Bernoulli Process (MMBP) cell streams is exactly analyzed. The probability mass function of queuing delay, the autocorrelation and power spectrum of delay jitter for this periodic cell stream are derived. The analysis is used to expose the behavior of delay jitter for a periodic cell stream through an ATM multiplexer in a bursty traffic environment. The simulation results indicate that the analytical results are accurate.     

ATM cell delay and loss for best-effort TCP in the presence ofisochronous traffic

This paper reports the findings of a simulation study of the queueing behavior of “best-effort” traffic in the presence of constant bit-rate and variable bit-rate isochronous traffic. In this study, best-effort traffic refers to ATM cells that support communications between host end systems executing various applications and exchanging information using TCP/IP. The performance measures considered are TCP cell loss, TCP packet loss, mean cell queueing delay, and mean cell queue length. Our simulation results show that, under certain conditions, best-effort TCP traffic may experience as much as 2% cell loss. Our results also show that the probability of cell and packet loss decreases logarithmically with increased buffer size     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

Bursty ATM user traffic allowed by a jitter tolerant leaky bucket and its impact on link utilization

In a network based on the asynchronous transfer mode (ATM), quality of service requirements have to be met even in the presence of users who send traffic as bursty as the policing device allows. For peak cell rate policing with a jitter tolerant leaky bucket, a periodic maximally bursty traffic pattern allowed by the leaky bucket is derived. The impact of this kind of bursty user traffic on the cell loss performance of the remaining sources is investigated by introducing, solving and applying the queueing model Geo(n) + P/D/1/K, where P stands for ‘periodic’. Taking bursty user traffic into account, it is shown that the maximal jitter or cell delay variation allocated to the user and tolerated by the leaky bucket is an important parameter for link utilization. The results help to answer the question under which conditions a shaping function is needed in conjunction with the usage parameter control function.     

NN based ATM cell scheduling with queue length-based priorityscheme

The asynchronous transfer mode (ATM) is the choice of transport mode for broadband integrated service digital networks (B-ISDNs). We propose a window-based contention resolution algorithm to achieve higher throughput for nonblocking switches in ATM environments. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line (HOL) blocking when first-in first-out (FIFO) queueing is employed. To resolve this problem, we employ bypass queueing and present a cell scheduling algorithm which maximizes the switch throughput. We also employ a queue length based priority scheme to reduce the cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of cell delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates (CLRs) at a given buffer size. As the cell scheduling controller, we propose a neural network (NN) model which uses a high degree of parallelism. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given CLR become smaller than those of other approaches based on sequential input window scheduling or output queueing     

Performance evaluation of multiple input-queued ATM switches withPIM scheduling under bursty traffic

In this letter, we analyze the performance of multiple input-queued asynchronous transfer mode (ATM) switches that use parallel iterative matching (PIM) for scheduling the transmission of head-of-line cells in the input queues. A queueing model of the switch is developed under independently, identically distributed, two-state Markov modulated Bernoulli processes bursty traffic. The underlying Markov chain of the queueing model is a quasi-birth-death (QBD) chain. The QBD chain is solved using an iterative computing method. Interesting performance metrics of the ATM switch such as the throughput, the mean cell delay, and the cell loss probability can be derived from the model. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is briefly discussed     

N*DPT/D/1排队系统分析

多路离散周期串到达、单个服务台定长服务排队系统,是在研究CBR业务下ATM网络中间节点性能时所遇到的一种排队模型。在有线ATM网的CBR业务接进无线ATM网时也会遇到这种排队模型。本文分析了这一排队系统,得到了其队长剩余分布的计算公式。     

Buffer losses vs. deadline violations for ABR traffic in an ATM switch: A computational approach

The B‐ISDN will carry a variety of traffic types: the Variable Bit Rate traffic (VBR), of which compressed video is an example, Continuous Bit Rate traffic (CBR), of which telemetry is an example, Data traffic, and Available Bit Rate traffic (ABR) that represents aggregate data traffic with very limited guarantees on quality. Of these, VBR and CBR have timing constraints and need synchronous bandwidth; data traffic is relatively delay insensitive. In this paper, we consider the VBR, Data and ABR traffic types and obtain the cumulative distribution function (cdf) of the queueing delay experienced by a burst of ABR traffic in the output buffer of an ATM switch. The cdf is used to trade off buffer loss probabilities against deadline violation probabilities through adjusting the buffer size and (delay) deadline values. Large buffers result in low losses but queueing delays can become excessive and cause a high level of deadline violations. Both losses and violations are detrimental and an operating point must be chosen to achieve a balance. In this paper we study the nature of the trade off. We develop a stochastic Petri net model assuming periodic burst arrivals for VBR and Poisson arrival processes for the Data and ABR traffic types at the burst level, and solve the model analytically (numerically) using a decomposition approach. This decomposition, along with the inherent decomposability of the tagged customer approach for obtaining the cdf opens up a possibility of carrying out fast computations using a parallel machine for selecting the operating point each time that a call is admitted. This revised version was published online in June 2006 with corrections to the Cover Date.     

Buffer sizing in an ATM switch for both ATM and STM traffics

Specific queueing models are derived in order to size the buffers of ATM switching elements in the cases of ATM or STM multiplexed traffic. Buffering is performed either at the outputs or in a central memory for ATM multiplexed traffic; for STM multiplexed traffic, buffers can also be provided at the inputs. The buffer size is chosen in order to ensure a loss probability in the switch smaller than 10^?10. It is shown that the buffer size per output in the case of central queueing is smaller than the buffer size in case of output queueing for both ATM and STM multiplexed traffics. Moreover, for STM multiplexed traffic, buffer sizes are identical for input and output queueing. Lastly, it is pointed out that buffers used for STM multiplexed traffic should be 4 to 20 times larger than the corresponding buffers for ATM multiplexed traffic.