Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A highly sensitive thermosensing CMOS Circuit Based on self-biasing circuit technique

A thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed. The circuit is based on a self-biasing circuit technique and uses the temperature-sensitive characteristics of MOSFETs operating in the subthreshold region. To develop this sensor device, a method to analyze self-biasing circuits, which is different from a conventional one, was employed. This method is useful for understanding the self-biasing circuit operation. A temperature sensor device makes use of a MOSFET resistor's transition from a strong inversion to a weak-inversion or subthreshold operation. The temperature at which the transition occurs can be set to a desired value by adjusting the parameters of MOSFETs in the circuit. The sensor LSI can be made using a standard CMOS process and can be used as over-temperature and over-current protectors for LSI circuits. Copyright © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

A systematic class AB state space synthesis method based on MOSFET square law and translinear square‐root cells

A new state space Class AB synthesis method for the design of square‐root domain filter based on the MOSFET square law is proposed in this study. Those circuits designed by the proposed Class AB systematic synthesis method have the advantages of Class AB circuit structure and translinear circuits. Two alternative design procedures were suggested for designing new circuits. Proposed synthesis technique is applied for designing of a first order all‐pass filter and a third order low‐pass filter. Circuits are simulated in PSpice using 0.35 µm CMOS technology parameters. Time domain and frequency domain analysis of the proposed filters are performed, and simulation results of those are also presented. The simulation results show that the proposed synthesis technique is appropriate for the design of different types of filters and has the advantages of Class AB circuit structure. Copyright © 2015 John Wiley & Sons, Ltd.     

Low energy/delay overhead level shifter for wide‐range voltage conversion

Multi‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

A 0.15‐μm CMOS baseband LSI employing sleep mode with clock‐offset compensation for M2M wireless sensor networks

This paper describes a wireless baseband large‐scale integration (LSI) that contains a sleep management circuit. The sleep manager performs the sleep‐clock offset compensation and enables a wireless terminal (WT) with a typical crystal oscillator (XO) to remain in sleep mode for a long period while maintaining synchronization with the access point. Lab experiments show that the sleep period reaches 512 s and that, with intermittent operation, the WT maintains synchronization with the access point for 10 days. The LSI's average current consumption is as low as 11 μA for a 128‐s sleep period. A wakeup detection circuit is also implemented in the LSI. This circuit performs paging control instead of a microprocessor unit (MPU) and this helps to reduce current consumption in the MPU and the flash read only memory (ROM). The single‐chip baseband LSI is fabricated using 0.15‐μm CMOS technology. It is 4.6 mm × 4.2 mm in area and consumes 4.0 μA for sleep operation. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A reduction technique of large‐scale RCG interconnects in the complex frequency domain

High‐speed digital LSI chips usually consist of many sub‐circuits coupled with multi‐conductor interconnects embedded in the substrate. They sometimes cause serious problems of the fault switching operations due to the time‐delays, crosstalks, reflections, etc. In order to solve these problems, it is very important to develop a user‐friendly simulator for the analysis of LSIs coupled with interconnects. In this paper, we consider a large‐scale gate‐array circuit coupled with multi‐conductor RCG interconnects. At first, we propose a new method for calculating the dominant poles of the impedance matrix, which give the large effects to the transient response. The corresponding residues are estimated by the least squares method. Using these poles and residues, the input–output relation of each interconnect can be described by the partial fractions. After then, the interconnect is replaced by the equivalent circuit realizing the partial fractions. In this way, we can easily develop a user‐friendly simulator familiar with SPICE. We found from many examples that the good results can be obtained using only few dominant poles around the origin. Furthermore, the reduction ratio of our method is very large especially for large scale interconnects. Copyright © 2004 John Wiley & Sons, Ltd.     

Stability analysis of wideband linear bipolar varactor‐controlled oscillator with two‐coupled resonant circuits

Theoretical analysis of the stability conditions of the steady‐state operation modes and tuning bandwidth characteristics of bipolar self‐biased varactor‐controlled oscillator (VCO) with two‐coupled resonant circuits are presented. The recommendations at the choice of the circuit and varactor parameters for a linearization of the wideband tuning frequency characteristics under free‐running stable oscillation conditions are given. Highly linear octave‐band tuning operation was found to be possible using hyper‐abrupt varactors in two‐coupled resonant circuits VCO. Numerical and experimental results verify the validity of the design approach described. Copyright © 1999 John Wiley & Sons, Ltd.     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

A study of three‐dimensional observation of prebreakdown phenomena in dielectric liquids

This paper presents a new method which visualizes the high‐speed three‐dimensional images of prebreakdown streamers in dielectric liquids. A new optical system, having two crossed light axes to observe the needle tip from different directions, was designed. The shadowgraphic images from these two directions were combined through a beam splitter and focused on the photo‐cathode of an image converter camera. The photograph taken by this high‐speed shadowgraph system was reconstructed to three‐dimensional images using an image scanner and a computer. Using this system, the growth and decay processes of the streamer in cyclohexane were investigated. © 1999 Scripta Technica, Electr Eng Jpn, 128(4): 9–15, 1999     

Novel current‐source multilevel inverter driven by single gate drive power supply

This paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20475     

Electric double‐layer capacitor module with series‐parallel reconfigurable cell voltage equalizers

When electric double‐layer capacitors (EDLCs) are connected in series, a cell voltage imbalance occurs due to nonuniform cell properties. Cell voltage imbalance should be minimized to prolong cycle lives and maximize the available energy of cells. In this study, we propose a series‐parallel reconfigurable cell voltage equalizer that is considered suitable for energy storage systems using EDLCs instead of traditional secondary batteries as the main energy storage sources. The proposed equalizer requires only EDLCs and switches as its main circuit elements, and it utilizes EDLCs not only for energy storage but also for equalization. An equivalent circuit model using equivalent resistors that can be regarded as an index of equalization speed is developed. Current distribution and cell voltage imbalancing during operation are quantitatively generalized. Experimental charge–discharge tests were performed on the EDLC modules to demonstrate the performance of the cell voltage equalizer. All the cells in the modules could be charged/discharged uniformly even when a degradation‐mimicking cell was intentionally included in the module. The resultant cell voltage imbalances and current distributions were in good agreement with those predicted by mathematical analyses. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(4): 38–50, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21287     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

Converter Using SiC‐MOSFET for Ultra‐High‐Speed Elevator

In this study, we developed a converter based on SiC (Silicon Carbide)‐MOSFET for use in ultra‐high‐speed elevators, with a reduced volume of 15% compared with the conventional converter. We succeeded in reducing the power loss of the converter unit by 56% compared to the conventional converter in one round trip under high temperature condition. Recently, because of their useful characteristics, wide‐gap semiconductors, such as SiC and GaN, have gained considerable attention for use in various applications in the power electronics systems. Therefore, we studied the use of a converter in elevator systems based on SiC‐MOSFET. We used a 1200 V/800 A SiC‐MOSFET module for the converter unit. We developed a prototype of the converter unit and the control panel by applying for the SiC‐MOSFET module for an ultra‐high‐speed elevator. As a result, the setting area of the control panel (main part) becomes less than 43% of the conventional panel. We tried to demonstrate the working of a 68‐kW elevator by applying the prototype control panel. Because of the characteristic of the switching loss of SiC‐MOSFET, the power loss of the converter unit has almost no dependence on temperature. An energy‐saving effect of approximately 17% was achieved in the total elevator system in one round trip under high‐temperature condition.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.