A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.     

Circuit modeling for ultra‐wideband Tx‐Rx antenna systems based on frequency domain S‐parameters

This paper presents a circuit modeling procedure for Ultra‐wideband (UWB) Tx‐Rx antenna systems based on frequency domain S‐parameters. The modeling used an existing two‐port network's model consisting of four SPICE analog behavioral modules. The accuracy of the model has been validated by comparing its transient response with the measurement result using an oscillograph. This model can be used for the co‐design of the UWB Tx‐Rx antenna system with transmitters and receivers in circuit simulators. In the study, Tx‐Rx antenna systems using planar bow‐tie antenna and horn antenna with ultra‐wide bandwidths are used as examples. Copyright © 2010 John Wiley & Sons, Ltd.     

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley & Sons, Ltd.     

IO circuit design for 2.5D through‐silicon‐interposer interconnects

This paper presents four topologies of voltage‐mode un‐terminated IO cells in 28‐nm CMOS for single‐ended rail‐to‐rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design‐space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre‐emphasis and slew‐rate control. The transmitter (TX) embeds pre‐emphasis to enhance high‐frequency components of the signal for longer low‐pass natured channels. The TX also implements slew‐rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level‐shifting capability embedded in the receiver (RX) enables multi‐technology interfacing where different dies are signaling at their core voltages (range: 0.7 V–1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty‐cycle distortion with 700 μW at 500 MHz/0.8‐V‐signaling on the channel with jitter of 20 ps, ±10% duty‐cycle distortion with 1.8 mW at 1Gbps/0.9‐V signaling with jitter of 20 ps, ±10% duty‐cycle distortion with 2 mW at 2Gbps/0.7‐V signaling for 1‐V receiver core voltage with a jitter of 10 ps. Copyright © 2016 John Wiley & Sons, Ltd.     

Development of radio frequency transmitters including on‐chip antenna for intelligent human sensing systems

This paper presents the essentials of the development of an integrated smart microsensor system that has been developed to monitor the motion and vital signs of humans in various environments. Integration of RF transmitter technology with complementary metal‐oxide‐semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize wireless smart microsensors for the monitoring system. Sensors for the measurement of body temperature, perspiration, heart rate (pressure sensor), and motion (accelerometers) are candidates for integration on the wireless smart microsensor system. In this paper, the development of radio frequency transmitter (RF) that will be integrated on wireless smart microsensors is presented. A voltage controlled RF‐CMOS oscillator (VCO) has been fabricated for the 300‐MHz frequency band applications. Also, spiral inductors for an LC resonator and an integrated antenna have been realized with a CMOS‐compatible metallization process. The essential RF components have been fabricated and evaluated experimentally. The fabricated CMOS VCO showed a conversion factor from voltage to frequency of about 81 MHz/V. After matching the characteristic impedance (50 Ω) of the on‐chip integrated antenna and the VCO output, more than 5 m signal transmission from the microchip antenna has been observed. The transmitter showed remarkable improvement in transmission power efficiency by correct matching with the microchip antenna. Essential technologies of the RF transmitter for the wireless smart microsensors have been successfully developed. Also, for the 300‐MHz band application, the integrated RF transmitter, with the CMOS oscillator and the on‐chip antenna, has been successfully demonstrated for the first time. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Low energy/delay overhead level shifter for wide‐range voltage conversion

Multi‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley & Sons, Ltd.     

A reduction technique of large‐scale RCG interconnects in the complex frequency domain

High‐speed digital LSI chips usually consist of many sub‐circuits coupled with multi‐conductor interconnects embedded in the substrate. They sometimes cause serious problems of the fault switching operations due to the time‐delays, crosstalks, reflections, etc. In order to solve these problems, it is very important to develop a user‐friendly simulator for the analysis of LSIs coupled with interconnects. In this paper, we consider a large‐scale gate‐array circuit coupled with multi‐conductor RCG interconnects. At first, we propose a new method for calculating the dominant poles of the impedance matrix, which give the large effects to the transient response. The corresponding residues are estimated by the least squares method. Using these poles and residues, the input–output relation of each interconnect can be described by the partial fractions. After then, the interconnect is replaced by the equivalent circuit realizing the partial fractions. In this way, we can easily develop a user‐friendly simulator familiar with SPICE. We found from many examples that the good results can be obtained using only few dominant poles around the origin. Furthermore, the reduction ratio of our method is very large especially for large scale interconnects. Copyright © 2004 John Wiley & Sons, Ltd.     

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

A very low complexity impulse radio‐ultrawideband (IR‐UWB) transmitter suitable for balanced antenna is presented. This all‐digital transmitter employs the binary phase‐shift keying (BPSK) modulation scheme and eliminates the need for a balun. Also, a new Gaussian monocycle pulse generator is proposed which is used as impulse transmitted signal. The transmitter circuit was designed in 0.18‐μm complementary metal–oxide–semiconductor technology. The post‐simulation results show that the core chip size was only 0.02 mm². The output amplitude pulse yielded 150 mV peak‐to‐peak under a supply voltage of 1.8 V. Simulation results show that the transmitter consumes 8.5 pJ/pulse for 200‐MHz pulse repeating frequency. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

BiCMOS-Schaltung für Chip-internen adaptiven Leitungsabschluß

Übersicht Um Daten mit hoher Geschwindigkeit zwischen integrierten Schaltungen auszutauschen, muß die Verbindungsleitung zur Vermeidung von Störungen durch Reflexion mit ihrem charakteristischen Wellenwiderstand abgeschlossen werden. Der folgende Beitrag zeigt eine BiCMOS-Realisierung des Abschlußwiderstands mit hoher Genauigkeit auf dem Chip. Es wird ein Schaltungsprinzip vorgestellt, das die Anpassung an den tatsächlichen Wellenwiderstand der Übertragungsleitung ermöglicht und so minimale Reflexionen hervorruft. Messungen an einem Testchip bestätigen die Überlegungen.

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On-chip adaptive match-termination

Contents To exchange data between integrated circuits with high speed the transmission line needs to be match-terminated with its characteristic impedance in order to avoid interference caused by signal reflections. The following paper presents a BiCMOS realization of the termination resistance with high accuracy on the chip. A new circuit principle allows to adapt the internal termination to the effective characteristic line impedance and hence causes minimal reflections. Measurements of a testchip verify the operation.

     

RF transmitter using the dual‐pulse position modulation method for low‐power smart micro‐sensing chip

This paper presents a low‐power radio frequency (RF) transmitter using dual‐pulse position modulation (DPPM) for a smart micro‐sensing chip (SMSC) with sensors and large scale integrated circuit (LSI) on the same chip. The DPPM method is presented by a fixed pulse and a variable pulse within the same time frame. The distance between the fixed pulse and the variable pulse describes the amplitude of the input signal. A modulator and a ring oscillator were designed for the RF transmitter using the DPPM method. In the modulator, the pulse width modulation (PWM) signal is generated by the intersective method, and narrow pulses are extracted at the rising and falling positions of the generated PWM signal. The designed oscillator has the function of an oscillation controller. The RF transmitter was fabricated with sensors for an SMSC by complementary metal–oxide–semiconductor (CMOS) technology. The power consumption of the fabricated modulator was 4.5 mW. The power consumption of the proposed RF transmitter was measured as 7.0–7.3 mW at an input signal of 0.8–2.5 V. The RF transmitter using the DPPM method was able to reduce the power consumption by a maximum of 50.3% compared to a transmitter using the PWM method, because in the latter the dissipated power was 8.4–14.5 mW at the same input signal. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Adaptive impedance matching system for downlink of passive semi‐ultra wideband ultra‐high frequency radio frequency identification tag

The input impedance of ultra‐high frequency radio frequency identification tag varies with the received power on the chip. It will induce impedance mismatch between the receiver antenna and microchip, thus drastically affect the performance of communication. In this paper, a low cost and fully integrated automatic impedance matching system was presented to solve this problem. It consists of two control loops for independent control of the real and imaginary parts of impedance. The first control loop realizes resistance correction using a parallel LC tuning network, whereas the second control loop achieves reactance compensation using a series LC tuning network. In both loops, the mismatch information is detected for direct control of the variable elements, varactors, which are tuned in a sequential manner. For unambiguous control of the resistance correction, the sign of the intermediate reactance is used as a secondary control criterion to enforce operation into a stable region. The functionality of the proposed automatic matching system was verified for different input impedances of a specifically semi‐ultra wideband ultra‐high frequency radio frequency identification tag as the available input power varies. The results indicate that all matched impedances are clustered around the target impedance 50 + j0 Ω after acquisition of both loops. Copyright © 2012 John Wiley & Sons, Ltd.     

Some invariant sums of higher‐order sensitivities

In this paper, a new class of invariant sensitivity sums of higher‐order sensitivities is given. Sensitivity sums considered are relevant to a network function of general lumped time‐invariant circuits containing passive and active elements. It is assumed that the circuit is linear and consists of one‐port elements and two‐port elements only. A part of the one‐port elements is described by admittance parameters and the other part by impedance parameters. The rest of the one‐port elements are independent sources. Two‐port elements are only controlled sources. Hybrid matrix should describe functional relationships of the elements. Formulas for invariant sums of sensitivities of first, second, third, and fourth order are presented. Copyright © 2008 John Wiley & Sons, Ltd.     

Large-scale photonic integrated circuits

100-Gb/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb/s on a DWDM wavelength grid. Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs. The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption.     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.     

νMOS cellular‐automaton circuit for picture thinning and shrinking

In this study we propose a design for an LSI circuit that implements a cellular automaton. The cellular automaton is a parallel and distributed architecture device suitable for high‐speed image processing. To develop a cellular automaton LSI circuit, it is necessary to design small‐size unit cell circuits that can operate according to cell–cell interaction rules. We propose to use νMOSFET devices for such cell circuits. Template matching is implemented by combining multiple input νMOSFET circuits and inverters. A cell circuit was designed for image thinning and shrinking, and its operation was analyzed using a circuit simulator. It was demonstrated that high speed operation (up to 100 MHz clock frequency) can be obtained. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 41–48, 1999     

High‐frequency modeling of Cu‐graphene heterogeneous interconnects

One novel interconnect scheme consisting of both Cu and graphene sheet is proposed in this paper, with the advantages of both materials exploited greatly. It is shown that the introduction of graphene layers in such heterogeneous interconnect scheme can reduce its effective resistance and thereby improve its transmission performance. On the other hand, it is also demonstrated that both coated and double‐coated structures possess better electrical performance than that of the sandwich one at high frequencies, because the graphene is placed at the interconnect surface where current is crowded. With the help of Partial Element Equivalent Circuit method, together with equivalent circuit technique, the transmission characteristics of some Cu‐graphene interconnects are captured and compared with that of Cu wire, and the advantages of such heterogeneous interconnects can be enlarged with the advanced technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a CMOS multi‐rate adaptive continuous‐time equalizer based on power spectrum estimation

An adaptive continuous‐time equalizer for reliable short‐haul high‐speed serial communications is described in this paper. The adaptive equalizer uses the spectrum‐balancing technique to adapt its response to changes in the bandwidth, amplitude, and bit rate of the input signal. In this way, it is able to compensate the frequency response of a 1‐mm diameter step‐index plastic optical fiber, for lengths up to 50 m, and bit rates ranging from 400 Mb/s to 2.5 Gb/s. Experimental results are shown to demonstrate its feasibility. Copyright © 2017 John Wiley & Sons, Ltd.     

A power‐efficient 600‐mVpp voltage‐mode driver with independently matched pull‐up and pull‐down impedances

In this study, a large‐swing, low‐power voltage‐mode driver with independently matched pull‐up and pull‐down impedances is proposed. To achieve large swing and constant impedances during a transition, a P‐over‐N structure is implemented with regulators calibrating the impedances. Two regulators are dedicated to matching the pull‐up and pull‐down impedances by regulating the supply voltages of the driver and predriver, respectively. Because background impedance calibration loops are adopted to track the process, voltage, and temperature (PVT) variations, the proposed driver can operate properly without additional calibration time. To reduce the power consumption of the calibration loops, scaled replicas of the actual driver are used. Moreover, an analysis of design optimization for the proposed driver is presented. The proposed driver was fabricated in 65‐nm CMOS technology and verified at a 5‐Gb/s data rate. Measurement results show that the proposed driver has a voltage swing of 600 mV_pp and a horizontal eye opening of 0.5 UI. The prototype chip consumes 6 mW at a 1.0‐V supply. Copyright © 2014 John Wiley & Sons, Ltd.