High-mobility poly-Si thin-film transistors fabricated by a novelexcimer laser crystallization method

High-mobility poly-Si thin-film transistors (TFTs) were fabricated by a novel excimer laser crystallization method based on dual-beam irradiation. The new method can reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO₂/Si/glass substrate structure by means of laser irradiation not only from the front side but also from the back side. The grain size of poly-Si film was enlarged up to 2 μm. The field-effect mobilities of the TFT exceeded 380 cm²/V-s for electrons and 100 cm²/V-s for holes     

Short-channel amorphous-silicon thin-film transistors

Amorphous-silicon thin film transistors (TFTs) with submicrometer-long bottom-gate have been fabricated and their characteristics were evaluated. By the desirable effects of highly conductive source and drain of excimer-laser crystallized Si film, the mobility was hardly decreased from about 1.0 cm²/Vs for the 15-μm long TFT to about 0.9 cm²/Vs for the 0.5-μm long TFT. Detailed effects of the gate electrode thickness and length have been discussed on the TFT characteristics     

基于P-Type多晶硅TFT技术的集成型有源OLED驱动电路

低温多晶硅(LTPS:Low-temperature poly-Si)技术已经成为薄膜晶体管(TFT:thin film transistor)制作中最具吸引力的技术,并应用在AMOLED显示器中.P-type 技术能够简化 TFT 的制作过程.本文提出了一种应用 p-type 多晶硅 TFT的 AMOLED 驱动电路结构,包括栅极驱动器、数据驱动器以及像素阵列.数据驱动器采用分块方法,使得显示屏的输出线数大大减少.作者采用一种改进的 p-type 移位寄存器实现逐行选通的功能,并采用由 4 个 p-type 反相器级联构成的缓冲器来提高电路的驱动能力.为了验证上述电路结构的正确性,作者采用 HSPICE 软件进行仿真分析.结果表明,电路工作正常.利用韩国汉城国立大学及 Neo Poly 公司在多晶硅制作方面的优势,我们已经合作完成了应用上述电路结构的分辨率为96×3×128的有源 OLED 的制作.     

多晶硅TFTAMLCD的现状与前景

多晶硅有源矩阵液晶显示技术，特别是一体化多晶硅有源矩阵液晶显示技术以它独特的优点，越来越受到重视，并将在液晶显示领域中占有重要地位，但是，多晶硅有源矩阵液晶显示技术还存在一些问题，这也正是目前研究的主要内容，本文对低温下淀积高质量多晶硅薄膜技术；通过退火使非晶硅结晶为多晶硅技术；器件层转移技术；钝化技术；一体化技术以及多晶硅有源矩阵液晶显示的前景等进行了分析和讨论。     

Implementation and characterization of self-aligned double-gate TFTwith thin channel and thick source/drain

In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate and bottom-gate is achieved by a noncritical chemical-mechanical polishing (CMP) step. A thin channel and a thick source/drain region self-aligned to the two gates are realized in the proposed process. Simulation results indicate that the self-aligned thick source/drain region leads to a significant reduction in the lateral electric field arisen from the applied drain voltage. N-channel poly-Si TFTs are fabricated with a maximum processing temperature of 600°C. Metal-induced unilateral crystallization (MIUC) is used to enhance the grain size of the poly-Si film. The fabricated SADG TFT exhibits symmetrical bi-directional transfer characteristics when the polarity of source/drain is reversed. The on-current under double-gate operation is more than two times the sum of that under individual top-gate and bottom-gate control. High immunity to short channel effects and kink-free current-voltage (I-V) characteristics are also observed in the SADG TFTs     

Integration of organic LEDs and amorphous Si TFTs onto flexible andlightweight metal foil substrates

We report the integration of organic light emitting devices (OLEDs) and amorphous Si (a-Si) thin-film transistors (TFTs) on both glass, and unbreakable and lightweight thin stainless steel foil substrates. The doped-polymer OLEDs were built following fabrication of driver TFTs in a stacked structure. Due to the opacity of the steel substrate, top-emitting OLED structures were developed. It is shown that the a-Si TFTs provide adequate current levels to drive the OLEDs at video brightness (~100 cd/m²). This work demonstrates that lightweight and rugged TFT backplanes with integrated OLEDs are essential elements for robust and highly portable active-matrix emissive flat-panel displays     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

Active‐Matrix Field Emission Display with Amorphous Silicon Thin‐Film Transistors and Mo‐Tip Field Emitter Arrays

We present, for the first time, a prototype active‐matrix field emission display (AMFED) in which an amorphous silicon thin‐film transistor (a‐Si TFT) and a molybdenum‐tip field emitter array (Mo‐tip FEA) were monolithically integrated on a glass substrate for a novel active‐matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low‐voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a‐Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a‐Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for n⁺‐doped a‐Si etching with high etch selectivity to intrinsic a‐Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a‐Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a‐Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low‐voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

A novel self-aligned double-gate TFT technology

In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate (TG) and bottom-gate (BG) is realized by a noncritical chemical-mechanical polishing (CMP) step. An ultrathin channel and a thick source/drain, that allow better device performance and lower source/drain resistance, are also automatically achieved. N-channel poly-Si TFTs are fabricated with maximum processing temperature below 600°C. Metal induced unilateral crystallization (MIUC) is used for poly-Si grain size enhancement. The fabricated SADG TFT exhibits symmetrical bidirectional transfer characteristics when the polarity of source/drain bias is interchanged. The on-current under double-gate operation is more than two times the sum of that under TG and BG operation     

Bottom-gate poly-Si thin film transistors using XeCl excimer laserannealing and ion doping techniques

High mobility bottom-gate poly-Si thin film transistors (TFTs) have been successfully fabricated on a hard glass substrate using XeCl excimer laser annealing and ion doping techniques. The authors used an a-Si:H film which is deposited by a plasma-enhanced chemical vapor deposition (PECVD) as a precursor film, and then they crystallized the a-Si film by XeCl excimer laser annealing. The maximum field effect mobility and grain size obtained were 200 cm²/V-s (n-channel), and 250 nm, respectively. The poly-Si TFTs showed excellent transfer characteristics, and an ON/OFF current ratio of over 10⁶ was obtained. Successful control of the threshold voltage within 4 V using an ion doping technique is also demonstrated     

High-quality polycrystalline Si TFTs fabricated on stainless-steelfoils by using sputtered Si films

We have developed a low-temperature fabrication process (⩽ 200°C for high-quality polycrystalline Si thin-film transistors (poly-Si TFTs) on flexible stainless-steel foils. The fabrication processes is realized through sputter deposition of thin films, including active-Si and gate-SiO₂ films, crystallization of Si films by KrF excimer laser irradiation, and inductively coupled plasma hydrogenation. High-quality n- and p-channel poly-Si TFTs are successfully fabricated without suffering from problems of substrate bending, film ablation, or cracking in films. The resulting n- and p-channel poly-Si TFTs showed mobilities of 106 and 122 cm²/V·s, respectively. This paper describes the deposition and properties of the sputtered Si films and the fabrication process and electrical characteristics of the poly-SiTFTs     

A new bottom-gated poly-Si thin-film transistor

We have proposed and fabricated the new bottom-gated poly-Si TFT with a partial amorphous-Si (a-Si) region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the reverse leakage currents are decreased significantly in the new poly-Si TFT compared with conventional one. This reduction is due to the suppression of field emission currents by local a-Si region like that of a-Si TFTs while the ON currents are kept almost the same due to the considerable inducement of electron carriers in the short a-Si channel by the positive gate bias     

Characteristics of low-temperature poly-Si TFTs on Al/glasssubstrates

The low-temperature poly-Si TFTs described here were fabricated on the Al/glass substrates by anodic oxidation of Al. An Al layer on glass substrates can be used to control threshold voltage, improve stabilities, and suppress the temperature rise due to self-heating. The Al layer on glass, thus assuring the improved reliability of displays, using this type of TFT, effectively suppressed the self-heating effect of poly-Si TFTs on glass. The threshold voltage of a TFT with an Al layer was more stable than that without an Al layer. These results were supported by numerical analysis     

低温多晶硅TFT技术的发展

本文综述低温多晶硅（LTPS）TFT技术的最新进展情况。该技术目前的研究前沿是：（1）制作高性能的TFT；（2）在柔性衬底上制作LTPS TFT；（3）驱动有机发光器件的TFT；（4）LTPS TFT的新应用。同时还展望了LTPS TFT技术的未来发展趋势。     

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal–oxide–semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.      

Process-independent analogue data driver for polysilicon TFT AMLCD

Polycrystalline silicon (poly-Si) thin film transistor (TFT) technology is very suitable for driving an active matrix LCD (AMLCD) panel as the driver circuit, and the panel can be integrated on the same substrate. This allows the entire display system to be thin and makes the concepts of ‘TV on wall’ and ‘sheet computer’ possible. However, the large variation of threshold voltage of poly-Si TFT across the wafer makes it difficult to obtain analogue amplifiers with constant gain and phase margin. In this paper, an analogue data driver for the poly-Si TFT AMLCD is proposed. An operational amplifier with a gate bias-voltage generation circuit for this analogue data driver, with characteristics independent of variations in threshold voltage, will be presented. In Hspice simulation, with threshold voltage varying from 2.5?V to 4.5?V, gain variations of the proposed amplifier were reduced from ±10?dB to ±0.2?dB and phase margin variations were reduced from 10° to 0.37° compared with typical operational amplifier design. This enables the analogue data driver for AMLCD to be implemented in poly-Si TFT technology.     

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of SiO2

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO₂ was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO₂ C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO₂ C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm²/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.