基于功率谱FFT的BPSK信号参数估计

针对低信噪比环境下二相编码(BPSK)信号参数估计的问题,该文提出一种基于功率谱 FFT 的信号参数估计算法.该算法根据信号功率谱傅里叶变换得到的幅度谱和相位谱与各参数之间的关系,实现 BPSK 信号的码元宽度、载频和码长估计.该算法对功率谱继续做傅里叶变换可以进一步消除噪声对估值的影响,更适合在低信噪比环境下实现参数的估计,且计算简单易于实现.仿真试验证明了该算法的准确性和抗噪性,在信噪比为-10 dB时BPSK信号的载频和码元宽度估计正确率分别比循环谱算法提高了9.9%和190.9%.     

各种规模集成电路

结构和电路设计是 CMOS 超大规模集成电路的两种最有效的功率减小方法。数学运算被应用于构造快速傅里叶变换(FFT)功率有效结构中。该结构采用异步电路技术,与其它 FFT 结构相比能明显降低功率。本文提出了一种比传统设计方法更明显降低功率的多速率信号处理技术和异步设计方式的算法;构造了一种完成该设计一部分的测试芯片,并做了功率比较。参6     

Hartley变换OFDM调制的可见光通信研究

针对正交频分复用(OFDM)可见光通信系统中存在高峰均功率比的问题，将预编码与迭代限幅滤波技术相结合应用于Hartley变换OFDM调制的可见光通信系统中，并对传统的采用FFT/IFFT限幅滤波的OFDM系统进行改进。根据建立的FHT的可见光OFDM系统模型，分别比较了不同方案下系统的频谱利用率、PAPR和误码率等性能，并分析了离散余弦变换和Hadamard矩阵预编码对PAPR的抑制作用以及FFT/IFFT、DCT/IDCT和FHT/IFHT三种不同变换方案的滤波性能。结果表明:FHT的可见光OFDM系统比FFT的OFDM系统的计算复杂度低、频谱利用率高；DCT预编码技术在克服系统PAPR及提升系统误码性能上更具优势；FHT/IFHT迭代限幅滤波的误码性能优于FFT/IFFT和DCT/IDCT。      

DIF-2FFT算法的矩阵形式的DLP计算模式

快速傅里叶变换(FFT)是减少离散傅里叶变换(DFT)计算时间的算法。而在无线/移动通信系统中无线通信算法和多媒体应用处理算法中存在大量的矩阵或向量运算,均可以由DLP计算实现。本文研究的FFT算法就存在大量的矩阵运算,通过对FFT矩阵算法的分析,本文提出了在DLP计算模式下通过阵列计算机来实现FFT的快速算法,在MATLAB仿真平台上进行了传统算法与改进之后算法的比较,提出了进一步减少运算时间的FFT并行算法。     

基于FFT频谱仿真的研究与设计

电力电子技术的关键知识点很多,电力电子技术的研究对象是功率处理和变换,电力电子技术离不开表征电能的电压、电流、频率、波形和相位等若干基本参数的控制与转换,快速傅里叶变换(简称FFT)是电工电子中计算离散傅里叶变换的一种重要的计算公式,提出了一种计算算法,频域分析的编程中以FFT算法为基础,在对时域波形进行采样后,经过FFT处理离散数据,最终得到相关量的振幅谱,并且对算法编程实现,仿真试验达到预期目的.     

基于交替投影的MIMO雷达最优波形设计

该文研究用于多输入多输出(MIMO)雷达的具有低相关旁瓣的恒模波形设计方法,这类波形可以抑制距离旁瓣遮蔽和不同信号回波之间的相互干扰。首先,根据非周期相关函数与功率谱(PSD)之间的傅里叶变换对关系,将波形的相关特性优化问题转换为功率谱优化问题;然后,基于功率谱拟合的思想,将设计波形的功率谱向理想波形功率谱逼近;最后,在时、频域交替投影的算法框架下,利用快速傅里叶变换(FFT)实现波形的优化设计。计算机仿真表明,该算法能够设计具有良好相关特性的MIMO雷达波形且运算效率较高。     

基于LMD-Teager变换的功率谱估计

局域均值分解(LMD)方法是一种新的自适应信号处理方法,Teager能量算子是求解信号瞬时能量的非线性操作算法,能有效提取信号的瞬时能量。结合这两种方法的优点,提出一种基于LMD-Teager变换的功率谱估计方法,给出了算法原理和步骤,讨论了功率谱估计的物理意义,并在与快速傅里叶变换(FFT)方法、小波变换对比的基础上,用短数据序列和非平稳信号进行了仿真验证。结果表明:该方法突破了FFT方法中对所分析的信号必须平稳的要求,更适合于非平稳信号的处理;且对数据长度的要求较傅里叶方法低,而其分析精度和分辨率优于传统的傅氏方法和小波变换。     

高基数快速傅里叶变换的实现

提高实现的并行性和实时性是目前FFT(快速傅里叶变换)研究的一个重点。介绍了在CPLD(复杂可编程逻辑器件)中实现高基数FFT的一种方法。以较低基数的FFT搭建高基数的FFT,大大提高了变换的速度。文中以基16 FFT的实现为例,介绍了以基2实现基16运算的过程,着重描述了运算核的设计以及数据的存储和调用。     

基于ADSP-TS201的大点数FFT实现

为了解决雷达信号处理中大点数脉压问题,将一维大点数FFT拆成二维实现。首先给出大点数FFT变换的数学原理,然后以96K点为例,介绍了其在通用处理器ADSP-TS201的实现过程。测试结果表明,所提出的处理方式不仅能正确实现大点数FFT变换,而且具有较好的实时性。     

基于CCS的FFT的设计与实现

给出了按时间抽取的基-2FFT设计流程图,并对使用CCS工具的FFT变换结果和使用C语言程序计算的FFT变换结果进行比较。结果表明,使用TI公司的函数库DSPLIB不仅编程方便,程序的可读性强,而且实现同样的功能时操作简单,应用开发时间相对较小。     

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

The problem of an efficient very large scale integration (VLSI) realization of the direct/inverse fast Fourier transform (FFT/IFFT) for digital subscriber line (DSL) applications is addressed in this paper. The design of scalable and very high-rate (VDSL) modem claims for large and high-throughput complex FFT computations while for massive and fast deployment of the xDSL family low-cost and low-power constraints are key issues. Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption. A programmable VLSI processor based on a FFT/IFFT cascade architecture plus pre/post-processing stages is discussed and characterized from the high-level choices down to the gate-level synthesis. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the power consumption exploiting the correlation of the FFT/IFFT coefficients and the statistics of the input signals. To this aim both frequency-division and time-division duplex schemes have been considered. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Synthesis results for a 0.18 μm CMOS standard-cells technology show that the processor is suitable for real-time modulation and demodulation in scalable full-rate VDSL modem (64-4096 complex FFT, 20 Msample/s) with a power consumption of few tens of mW. These performances are very interesting when compared to state-of-the-art software implementations and custom VLSI ones.     

1M点FFT算法的FPGA设计与实现

采用可编程门阵列（FPGA）实现FFT算法,增加了信号处理的实时性。针对高速宽带信号的谱分析,提出了一种采用FPGA计算1M点FFT的实现方法,并对运算结果进行了测试验证。该成果同样适用于窄带信号的细微特征分析。     

Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures

We present an efficient approach for the partitioning of algorithms implementing long convolutions. The dependence graph (DG) of a convolution algorithm is locally sequential globally parallel (LSGP) partitioned into smaller, less complex convolution algorithms. The LSGP partitioned DG is mapped onto a signal flow graph (SFG), in which each processor element (PE) performs a small convolution algorithm. The key is then to reduce the complexity of the SFG in two steps: 1. local reduction of complexity: the short Fast Fourier Transform (FFT) is used to perform the small convolution within the PE; and 2. global reduction of complexity: the short FFTs within the PEs are relocated to the global level, where redundant short FFT operations are eliminated. The remaining operation within the PEs is now a simple element-wise multiply-add. After a graph transform, the structure of the SFG kernel is recognized as a set of parallel small convolutions. If we use the short FFT to perform these short convolutions, we come to our final realization of the long convolution algorithm. The computational complexity of this realization is close to the optimum for convolutions, that is, O(N log N). Our approach is thus achieving this N log N –low without having to implement large-size FFTs. We use, instead, small FFT blocks. The advantage is that small FFT transforms are commercially available, and that they can even be implemented in single-chip VLSI architectures. Our final SFG is three dimensional and can be mapped efficiently onto prototype architectures or dedicated VLSI processors. We demonstrate the procedure in the paper by a design example: the implementation of a prototype convolution architecture that we designed for a real-time radar imaging system.     

Hardware architecture for an anti-traffic noise system

This work presents an energy efficient architecture for an anti-traffic noise system. The hardware is designed for a road side unit (RSU) in intelligent transportation systems. Fast Fourier Transform is the cornerstone for the suggested system. An ultra low power architecture for the FFT suitable for FPGA implementation is derived. Bit-widths for both data and twiddle factors are optimized for low-power. The architecture uses an efficient complex multiplier that has 25% less multiplications. An algorithm to compute the number of time-shared butterflies for a given FFT block size and a target throughput is elaborated. Finally synthesis results using fixed-point VHDL library and commercial IP are presented and compared with the proposed FFT processor.     

基于CORDIC的一种高速实时定点FFT的FPGA实现

本文论述了一种利用CORDIC算法在FPGA上实现高速实时定点FFF的设计方案。利用CORDIC算法来实现复数乘法，与使用乘法器相比降低了系统的资源占用率，提高了系统速度[1]。设计基于基4时序抽取FFT算法，采用双端口内置RAM和流水线串行工作方式。本设计针对256点、24位长数据进行运算，在XilnxSpartan2E系列的xc2s300e器件下载验证通过，完成一次运算约为12μs，可运用于高速DSP、数字签名算法等对速度要求高的领域。     

基于无线Wi—Fi的智能小车控制系统设计

设计了一种基于Wi—Fi的超低功耗远程智能小车控制系统.系统以STC89C52单片机作为主控芯片,采用Wi—Fi模块将视频模块采集到的小车的视频信号传输给智能终端,并将智能终端的控制信号发送给小车的控制核心—MCU,控制电机驱动模块实现对智能小车的控制,有效实现小车对陌生和危险环境的探索.结果显示,该设计可以实现有效距离的精准控制和实时视频的稳定传输.系统具有低功耗、低成本、运行可靠的特点,具有很好的实用价值和应用前景.     

基于单片机和DSP的被动声目标探测平台设计

设计完成了一种被动声目标探测通用平台。基于微功耗的MSP430单片机和低功耗的TMS320C5000数字信号处理器,配合低功耗四路同步采样A/D转换器、灵活的电源控制和丰富的外部接口,可满足目标探测系统的不同要求。系统具有体积小,功耗低,接口丰富等特点。样机经实际测试,达到了预期的设计目标。     

Efficient Power Management for Energy-Autonomous Wireless Sensor Nodes for Aeronautical Applications

Efficient power management is a key component for energy-autonomous wireless sensor nodes. Thermoelectric energy harvesting is a possible solution for powering such sensor nodes. In this paper, we present a power management circuit that has significant improvements compared with earlier versions. Advancements were made to the rectifier part and the storage controller. The improved rectification circuit is able to control the p-metal–oxide–semiconductor (p-MOS) transistors with a negative instead of zero voltage at the gate. Furthermore, modifications to enhance the total efficiency of the storage controller are applied. The storage controller is a direct current (DC)–DC converter and is controlled by a pulse frequency modulation signal, provided by a microcontroller. In the modified version, the microcontroller is always in low-power mode, and an external circuit is used to control the storage controller. Changes in the software are applied so that the microcontroller is always set in low-power mode. The runtime with and without a load are compared, and the overall self-discharge time is evaluated.     

MIPS/W8位低功耗嵌入式RISC MCU核的设计

介绍了一种8位低功耗嵌入式RISC MSC核的设计.该核采用哈佛结构,三级流水线,单周期指令,指令集与PIC16C57相兼容.本文还对系统结构设计及各单元模块设计进行了分析.     

多载波中的实数FFT及其离散Hartley变换实现

在OFDM／DMT多载波调制中，FFT为实数FFT（Real—Valued FFT），输入全部为实数，变换后的输出为偶函数即具有一定的共轭特性。相应地，IFFT为实数FFT的逆过程。实数FFT的实现与复数FFT具有很大的不同，文中提出了一种基于离散Hartley变换的实现方法，运算过程全部为实数过程，与复数FFT相比，所需的乘法、加法运算以及RAN的开销均大幅度降低。