可靠性寿命试验的动态截尾方法

为节省试验时间和资源，可靠性寿命试验通常采用定数截尾和定时截尾两种方法。但是它们有相同的不足，就是在试验结束后才进行数据分析，无法进行实时的动态控制。为解决这一问题．提出了寿命试验的动态截尾方法，利用该方法研究寿命服从指数型分布产品的可靠性试验．提出了试验动态截尾的数据处理模型及判据。该方法的思想可以推广应用于其它产品的可靠性试验与分析中。     

LED组件寿命评估方法的研究

由于LED技术的飞速发展,其应用产品不断扩大到人们生活的各个方面,因此LED产品的可靠性问题也日益受到人们的关注。在可靠性工程常用的寿命分布中,指数分布是应用广泛的一种分布,进入偶然失效期以后都可以认为产品失效分布是指数分布。LED产品的寿命试验有定时截尾和定数截尾2种方式,由于定数结尾需要较长的试验时间,因此采用定时截尾的试验方法来获取试验数据。给出了LED组件的寿命评估方法,该方法对LED模块和应用产品同样适用。     

Weibull分布下的系统可靠性评估方法研究

在Weibull分布的定时截尾样本中,对可靠性、可靠寿命和失效率这3种参数的验前分布及形状参数的验前信息进行了分析。论述了结合熵损失函数来求得系统可靠度及寿命的Bayes点估计和置信下限,为大型系统的可靠性评估提供了一种重要的理论依据。     

微型计算机可靠性验收试验探讨

可靠性试验是对产品的可靠性进行分析评价的一种手段。以微型计算机为研究对象,对其进行可靠性试验。试验采用定时截尾方法,分别采用点估计和区间估计的方法对平均无故障时间(MTBF)进行处理。通过对试验数据的分析,对微型计算机做出了较为客观的可靠性评估。     

可靠性试验样本量和截尾时间的计算

可靠性寿命试验中，一般都因受到费用和时间的限制，因此要用截尾试验获得信息，再据此对其可靠性进行统计推断，用非参数估计的方法探讨了进行可靠性试验的样本量或截尾时间的估计方法。     

一种电子设备贝叶斯可靠性评估的新方法

针对贝叶斯方法应用中后验参数的运算复杂性问题,提出了一种电子设备贝叶斯可靠性评估的新方法.基于工程实践中常见的先验信息建立失效率先验分布,通过随机采样构建设备寿命分布参数的离散联合先验分布,结合截尾试验数据,再通过二次随机采样得到分布参数的离散联合后验分布函数.通过实例给出了运算过程,并与其它贝叶斯运算方法进行了比较.结果表明,此方法在确保精度的同时可以大大简化计算过程,在电子设备可靠性评估中有较高的应用价值.     

接口混合集成电路长期工作寿命预计及验证

寿命试验常被用来评估集成电路等半导体器件的可靠性,为了节约试验时间,常采用加速寿命试验方法去评估集成电路产品的工作寿命。采用基于可靠性手册中器件失效率历史数据和基于失效物理模型两种方法对接口混合集成电路的长期工作寿命进行了预计及验证。首先,通过接口混合集成电路产品多批次寿命可靠性试验的历史数据计算出了电路工作寿命;然后,基于可靠性手册中器件失效率的历史数据、模型及其使用特性要素计算出产品的工作寿命。结果表明,两者较为接近;从而证明该类混合集成电路在加速寿命试验数据不够的情况下,采用基于可靠性手册中器件失效率数据对其进行寿命预测是可行的,为接口混合集成电路长期工作寿命评估提供了一定的参考。     

基于样本空间排序法的剩余寿命评估

主要讨论了不同定时截尾数据剩余寿命评估的问题。利用样本空间排序法对指数分布和威布尔分布下不同定时截尾数据的可靠性参数进行估计,并进一步将参数估计值代入建立的剩余寿命评估模型,求取产品的剩余寿命。结果证明样本空间排序法在样本量较少的情况下,精度满足要求。     

电子产品研制过程的可靠性管理

为建立闭环式可靠性管理,本文从如何确定可靠性参数和指标开始,对如何进行可靠性预计、如何确定定时截尾可靠性鉴定试验方案{T,C}和开展软件可靠性定量评估等方面进行了讨论。     

家用电器无故障定时截尾可靠性试验方案探讨

无故障定时截尾方案是针对故障率较低的家用电器产品的可靠性鉴定试验和验收试验方案,累计测试时间依据置信度确定,可接收状态为无故障或仅出现1个故障,试验方案编制简便和易以掌握,试验过程管理简单。按寿命服从指数分布的条件导出试验方法,同时将适用范围推广至寿命服从形状参数已知的两参数威布尔分布的条件。     

基于加速性能退化试验的板级可靠性评估

传统的可靠性评估方法一般基于失效寿命数据,而目前对于高可靠长寿命的电子产品,很难通过加速试验获得其失效寿命时间。为解决这一矛盾,将性能退化理论引入到传统可靠性评估中,提出了基于失效数据及加速性能退化的可靠性评估的新方法。应用某型雷达24V/2A稳压电源板加速性能退化试验进行验证,结果表明该方法用于高可靠长寿命电子装备的可靠性评估是正确有效的。     

Evaluating board level solder interconnects reliability using vibration test methods

In this paper, three types of accelerated test methods based on vibration loadings are conducted and compared for board level mechanical reliability evaluation. The first type is fixed frequency sine vibration. The second type is swept sine vibration within a narrow-band of frequency. And the third type is swept random vibration within a narrow-band of frequency. The PCB responses were recorded using a high speed strain data acquisition system. The eigenfrequency of test boards were obtained with the FFT (Fast Fourier Transform) of the strain data of the PCBs during vibration. The PCBs' responses under different tests are compared. The failure processes were monitored and characterized. Results show that the vibrating amplitude is highly dependent upon the frequency ratio. The variation of PCBs’ eigenfrequency may cause the difference of loading amplitudes for fixed frequency vibration, which reduced the repeatability and comparability. The other two vibration methods within a narrow-band frequency could eliminate the influence from the frequency variation of the test boards. The differences of these methods are the loading density and repetitions. The failure processes of the three types of test methods are similar. Four failure stages were found from collected failure data. Weibull plot results show the characteristic life of the solder interconnects which are verified with loading repetition.     

Correlation studies for component level ball impact shear test and board level drop test

This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop-impact on a portable electronic product. Two test methods are used in this study: the board level drop/shock test (BLDT) and the component level ball impact shear test (BIST). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes; and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses and three thermal aged conditions, were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters - number of drops to failure for BLDT and peak load, total fracture energy, and energy-to-peak load for BIST - were evaluated. The lack of universal correlations between the two test methods has ruled out the use of BIST for evaluating solder joint materials, but BIST is recommended as a test method for quality assurance in view of the strong correlation between the measured parameters and the failure mode. The total fracture energy parameter is preferred over the peak load and energy-to-peak load due to its higher sensitivity and reduced susceptibility to measurement error.     

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop impact experienced by a portable electronic product. Two test methods are used in this study: the board-level drop-shock test (BLDST) and the board-level high-speed cyclic bend test (HSCBT). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes, and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses, and three thermal aging conditions were investigated using these two test methods. Correlations between the two test methods were performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters—number of drops to failure for BLDST and number of cycles to failure for HSCBT—were evaluated. Finally, the potential of HSCBT as a test method for material selection and for bridging board-level and product-level tests was demonstrated through generation of board strain versus number of cycles to failure (S–N) curves of solder joints for six material systems, four bending frequencies, and two test temperatures.     

Accelerated life tests at higher usage rates

Accelerated life tests are extensively used to provide quickly the information about the life distributions of products. Test units are subjected to elevated stresses which yield shorter lives. For some products whose life is defined by usage, e.g., mileage and cycles, test units are also run at higher usage rates (UR) to compress the test time. This paper presents a method for testing products at both higher stress levels, and UR. Censoring time is pre-determined and fixed, while censoring usage is a function of UR. A UR effect model is proposed to describe the dependence of usage to failure (UTF) on UR. The relationship between UTF, and stress and UR is established, and used to estimate the UTF distribution at design stresses and usual UR. The model parameters are estimated by maximum likelihood method. The best compromise test plans, which choose the UR, stress levels, and sample sizes, are devised by minimizing the asymptotic variance of the estimator of a life percentile at design stresses and usual UR. The efficiency, and sensitivity of the test plans are evaluated. The results show that the test plans are efficient, and robust.     

融合GJB/Z299C和制造商维修数据的可靠性预计方法研究

目前针对电子产品的可靠性预计结果仍存在精度不够、结果偏差大的问题。本文分别讨论了GJB/Z299C预计方法和制造商维修数据预计方法偏差大的问题,并指出其原因。但同时两种预计方法的模型都存在鲜明的优点,因此,通过构建一种失效率修正系数,将这两种方法有效的结合起来,形成一种新的模型,即利用改模型对电子产品进行可靠性预计,其结果更加准确度,最后用实例验证了方法的有效性。     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Copper wire interconnect reliability evaluation using in-situ High Temperature Storage Life (HTSL) tests

This paper describes the use of in-situ High Temperature Storage Life (HTSL) tests based on a four point resistance method to evaluate Cu wire interconnect reliability. Although the same set up was used in the past to monitor Au–Al ball bond degradation, a different approach was needed for this system. Using conventional statistical methods of failure probability distributions and a fixed failure criterion were found to be unsuitable in this case. Besides this, tests usually take very long until a sufficient percentage of the population have failed according to that criterion. A simple physical model was used to electrically quantify ball bond degradation due to the prevailing failure mechanism in a substantially smaller amount of test time. The method enabled the determination of activation energies for a number of moulding compounds and is extremely useful for a fast screening of such materials regarding their suitability for Cu wire.     

电源管理IC失效模式验证及定位方法

电源管理集成电路(IC)的自动测试机(ATE)测试故障主要包括连续性失效、直流参数测试失效、交流参数测试失效和功能测试失效.ATE测试适用于大规模量产的不良产品的筛选,但是将ATE测试结果直接应用于失效分析依然存在覆盖局限性问题.针对不同功能测试结果,采用了不同的失效模式验证和分析方法.综合运用I-V曲线测试仪、示波器、函数发生器等仪器进行失效模式验证;使用微光显微镜、光诱导电阻变化仪器进行缺陷的失效定位;并借助电路原理图、版图进行故障假设;分析由过电应力、静电放电损伤、封装缺陷等导致的物理损伤;最终揭示了电源管理IC功能失效的主要原因.