镍金表面上LP封装中央焊盘焊点空洞控制

随着产品小型化的发展,微小LP封装器件的应用越来越广泛,其中中央焊盘焊点空洞率成为影响产品功能的关键因素.主要研究镍金表面处理印制电路板上LP封装器件中央焊盘锡铅焊点空洞问题.介绍了焊点空洞的产生机理、焊接工艺难点及空洞控制方法,提出了优化焊盘设计、优化模板开孔设计、强化焊膏使用控制、控制焊膏印刷精度、控制贴装精度和优化焊接工艺参数等六大保证措施.经试验验证,同时采取6项措施后,有效地控制了镍金表面处理的PCB上LP封装器件的中央焊盘焊点空洞问题.     

焊膏涂覆工艺选择对CCGA焊接可靠性的影响研究

首先从焊膏材料特性、涂覆形貌、贴片形貌、焊接形貌等方面,对比研究了喷印和丝印两种焊膏涂覆工艺;并通过CCGA器件焊接对比分析了焊膏涂覆选择对焊点可靠性的影响。结果表明:焊膏材料特性包括粒径、合金含量和焊膏黏度等对涂覆工艺的选择至关重要。在涂覆形貌上,丝印焊膏因其颗粒度大,助剂少,相比喷印焊膏有更好的形貌稳定性。采用KH-7700显微镜、X-ray探测和金相剖切对焊接结果进行检验,两种涂覆工艺及其材料均呈现良好的焊接形貌和均匀连续的金属间化合物结构,证明了两种焊膏涂覆工艺焊接CCGA器件的可靠性。     

BGA无铅焊点零空洞缺陷控制研究

在无铅BGA封装工艺过程中,通过不同组分的BGA焊球合金与焊膏合金组合焊接、焊膏助焊剂活性剂不同配比及其不同再流焊接条件等实验,对焊料合金和助焊剂配比、再流焊接峰值温度、再流保温时间等参数变化,以降低BGA焊点空洞缺陷进行了研究。结果表明选用相同或相似的BGA焊球和焊膏合金组合焊接、选用活性强的焊膏、选择焊接保温时间较长均有助于降低BGA焊点空洞缺陷产生的几率和空洞面积,BGA焊点最佳再流焊接峰值温度为240℃,当峰值温度设置为250℃时,BGA焊点产生空洞缺陷几率会比240℃高出25%～30%。     

微带板高钎透率大面积钎焊技术研究

研究了不同焊接工艺方法、焊膏量以及焊接材料(Sn37Pb、Sn3.5Ag)对微带板与垫板之间大面积钎焊质量的影响。X光检测结果表明,采用优化后的焊接工艺方法及焊膏量,微带板与垫板之间大面积钎焊钎透率可达95%以上;焊点微观组织分析结果表明,Sn3.5Ag焊点内部存在较大尺寸的脆性金属间化合物相,对焊点的力学性能有不利影响,建议使用Sn37Pb焊料进行微带板的焊接。     

铝合金熔化极电弧点焊及其在雷达研制中的应用

熔化极电弧点焊是在熔化极自动焊基础上发展起来的一项焊接种工艺。美、日、苏等国在六十年代应用于火箭、飞机、机车车辆、建筑安装等许多工业部门。本文主要讨论焊接工艺及生产应用实践,并简要介绍焊接设备。对下板不完全熔透焊点的拉剪强度波动进行了实验,研究了焊点周围的黑色沉积物和焊点裂纹。NDAI—300型多用焊机成功地用于雷达研制,焊接了巨型加载波导、天线反射面骨架、全铝雷达设备车车箱蒙皮及铝机柜等。     

CCGA焊接工艺与可靠性研究

本文针对CCGA的焊盘设计、贴装设计、回流焊接曲线设计进行了优化。通过装联后的焊点经过X-RAY、金相分析等检测手段,CCGA焊点质量符合要求。通过加固设计,使得CCGA焊点满足可靠性要求。     

细间距焊接技术应用研究

首先简要分析了表面组装技术（SMT）细间跨焊接的工艺方法,然后重点讨论了焊盘设计、丝印、贴片、再流焊各种参数对焊接质量的影响,以及对不良焊点的分析及解决办法,最后简要分析了再流焊焊接理论。     

厚膜电路丝焊工艺中的“闭环”研究

现在在标准的和一些细节距丝焊应用中，批量生产时检查焊点质量的方法仍旧一样。现在很多工业所要求的用于确定键合质量的检验方法已证明可以接受并且可靠，它们是焊球剪切、测量焊球直径和焊丝拉力。这些方法可以接受，但是随着半导体领域趋向超细节距丝焊，这些传统方法所得到的数据可能还不够。随着每个电路键合焊丝的增多和焊点尺寸的减小，焊机、焊头、材料和方法之间的影响变得越来越敏感。本文采用“闭环”丝焊方法来研究分析。     

印制电路板焊点激光检测工艺研究

彩电和收录机、计算机等电子产品整机可靠性,很大程度上依赖于印制电路板的焊接质量,尤其是基板焊接过程中出现的假焊、虚焊现象,对整机质量危害最大。为了提高电子产品整机质量,必须对生产流水线上的锡焊工序进行严格地工艺监控。为防止虚假焊点对整机的危害,必须大生产过程中将虚假焊点检查出来并进行补焊。目前国内各电子整机生产厂家,普遍使用人工目视检查法和电气检查法检查焊点质量,其最大的缺点在于无法有效可靠地检查出焊点内部隐藏的缺     

埋头焊接的可靠性

埋头焊接是针对通孔插装元器件的一种特殊焊接方法.介绍了埋头焊接的优点,通过UG软件建立了电路板和焊点的三维有限元模型,利用焊点在近似试验载荷条件下的应力应变三维有限元数值模拟,就"先剪后焊"埋头焊接方法形成的焊点和普通焊点强度做了对比,给出了焊点的应力变化,并结合振动分析试验、温度循环试验和基于2D图像的X射线检测和分析,证明了埋头焊接方法应用的可行性.     

多线切割工艺断线问题的分析

在多线切割工艺中,镀铜金属线对硅单晶切割片的质量有着重要影响,成为多线切割工艺需要控制的重要辅料。断线问题一直是困扰多线切割工艺人员的主要问题之一,一直得不到有效的解决,从材料、设备、工艺以及人员等多个视角对断线问题进行了分析,并给出相应的解决措施。     

Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

Power and Interface Features of Thermosonic Flip-Chip Bonding

Driving voltage and current signals of piezoceramic transducer were measured directly by using digital storage oscilloscope, and interface microcharacteristics of the specimens of flip-chip bonding were inspected by using a transmission electron microscope. Results show such a trend that power curves of badly bonding were much lower than that of hard bonding, and indicated a monitoring system of ultrasonic bonding reliability. The acceleration of ultrasonic vibration was about several ten thousand times as acceleration of gravity, which activates dislocations inside the metal crystalline lattice which act as the fast diffusion channels. Dislocation diffusion is more prominent than the crystal diffusion when the temperature is low. Differing from thermal melting mechanism of the reflow bonding, the ultrasonic bonding is much faster than the reflow solder bonding.      

A new flip-chip bonding technique using micromachined conductivepolymer bumps

Using micromachining techniques with thick photoresists, a new conductive polymer flip-chip bonding technique that achieves both a low processing temperature and a high bumping alignment resolution has been developed in this work. By the use of UV-based photolithography with thick photoresists, molds for the flip-chip bumps have been patterned, filled with conductive polymers, and then removed, leaving molded conductive polymer bumps. After flip-chip bonding with the bumps, the contact resistances measured for 25 μm-high bumps with 300 μm×300 μm area and 400 μm×400 μm area were 35 mΩ and 12 mΩ respectively. The conductive polymer flip-chip bonding technique developed in this work shows a very low contact resistance, simple processing steps, a high bumping alignment resolution (<±5 μm), and a lower bonding temperature (~170°C). This new bonding technique has high potential to replace conventional flip-chip bonding technique for sensor and actuator systems, bio/chemical μ-TAS, optical MEMS, OE-MCM's, and electronic system applications     

金丝球焊的工艺质量统计控制

金丝球焊键合工艺作为主要的内部引线互连工艺技术，广泛应用于单片集成电路（IC）及厚薄膜混合集成电路（HIC）中。在批量生产中，其键合质量直接影响产品的可靠性，文章探讨了在批量生产中如何使用质量统计控制方法对金丝球焊键合工艺进行及时有效的调整控制，使其在批量生产中的质量一致性满足产品质量可靠性要求，提高产能和效率。     

Investigation of the characteristics of overhang bonding for 3-D stacked dies in microelectronics packaging

It is indicated that the impact and deflection of overhang die during overhang bounding process results in considerable impact of performance of bonding in this paper. Specifically, the deflection is unstable and up to 27 μm for the given parameters, which results in low shear force strength and low success rate of overhang bonding. To improve the performance of the overhang bonding, an effective and novel approach, overhang bonding with thick Al, is presented. The approach decreases hardness of bonding die, which makes the bonding die more compliant during bonding process than that in the traditional approach, thus the shear strength and bonding success rate of overhang bonding will be improved. Finally, effects of ultrasonic and force to overhang bonding indicates that excessively low or excessively high ultrasonic power results in weak bonding performances, and so did the force.     

Multichip optical hybrid integration technique with planarlightwave circuit platform

A two-step bonding technique for optical device assembly on a planar lightwave circuit platform was developed, which consists of a chip-by-chip thermo-compression prebonding step and a simultaneous reflow bonding step. The technique was used to realize multichip optical integration on the platform. The characteristics of the bonding technique were examined by investigating its strength and accuracy. The bonding accuracies in the horizontal and vertical directions were 1.1 and 0.8 μm, respectively, with high bonding strength. The technique was first applied to a 3 chip integrated transceiver module and the 136 fabricated modules exhibited good performance. The average coupling loss between the laser diodes and the waveguide was estimated to be 4.1 dB and stable characteristics were observed during 1200 cycle thermal shock tests between -40 and 85°C. Next, the two-step bonding technique was used for a 4 channel laser diode module on which 8 optical device chips were integrated and a low coupling loss was achieved of better than 4.2 dB which is as good as that of the 3 chip integrated optical modules     

Application of adhesive bonding techniques in hard disk drive head assembly

Current market conditions demand that hard disk drive (HDD) manufacturers adopt advanced technology in every area of drive design to improve drive capacity and performance and simultaneously reduce unit cost. Head stack suppliers in HDD industry are constantly working on high density interconnect technologies to provide faster and higher capacity and cheaper head stack components for disk drives. A low cost method to manufacture HDD head using anisotropic conductive film (ACF) bonding for flex-to-flex interconnection has been developed. This paper describes the process selection work among the current and the newly developed ACF bonding technologies. Bond pad design for ACF process using the finite element analysis method is introduced. Critical process bonding parameters are identified and characterized to give the optimal bonding conditions. Reliability evaluations on the final assemblies indicated that ACF bonding could give a very reliable electrical and mechanical interconnection.     

Bonding stress and reliability of high power GaAs-based lasers

GaAs-based lasers were bonded to oxygen-free high-conductivity (OFHC) copper heat sinks using a eutectic PbSn solder or a silver-filled conductive epoxy, and life tested. Epoxy-bonded devices were observed to have a larger failure rate on life test than solder-bonded devices. Bonding stress, as measured by the degree of polarization (DOP) of photoluminescence, was found to be the largest in epoxy-bonded devices. As well, the type of heat sink and bonding adhesive affected the stress in the laser material, with bonding stress increasing when there was a larger mismatch of coefficients of thermal expansion between the laser material, adhesive, and heat sink. Results suggested that heat sink material and bonding adhesive contribute to stress within the laser material and the resulting performance of the device     

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOS (ZSCCMOS) has been proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOS can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOS (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-/spl mu/m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.