Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

A power efficient buck‐boost converter by reusing the coil inductor for wireless bio‐implants

In this paper, a buck‐boost converter circuit for wireless power transfer via inductive links in bio‐implantable systems is presented. The idea is based on reusing the power receiver coil to design a regulator. This method employs five switches to utilize the coil inductor in a frequency other than the power‐receiving signal frequency. Reusing the coil inductor decreases the on‐chip regulator area and makes it suitable for bio‐implants. Furthermore, in the proposed technique, the regulator efficiency becomes almost independent of the coil receiving voltage amplitude. The proposed concept is employed in a buck‐boost regulator, and simulation results are provided. For a 10 MHz received signal with the amplitude variation within 3 ~ 6 V and with the converter switching rate of 200 kHz, the achieved maximum efficiency is 78%. The proposed regulator can also deliver 10 μA to 4 mA to its load while its output voltage varies from 0.6 to 2.3 V. Simulations of the proposed converter are performed in Cadence‐Spectre using TSMC 0.18 μm CMOS technology. Copyright © 2017 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

Wide‐band divide‐by‐2 injection‐locked frequency divider using MOSFET mixers DC‐biased in subthreshold region

A novel wide locking range divide‐by‐2 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18‐µm 1P6M CMOS process. The divide‐by‐2 ILFD is based on a cross‐coupled voltage‐controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56 mW. The die area is 0.839 × 0.566 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Power‐efficient burst‐mode RF transmitter based on reference‐adaptive multilevel pulse‐width modulation

Burst‐mode operation of power amplifier (PA) based on multilevel pulse‐width modulation (MPWM) has been frequently discussed as a potential solution to achieve higher efficiency in radio frequency (RF) transmitters. In this paper, a novel multilevel PWM modulator is proposed that utilizes adaptive triangular reference waveforms. As compared with conventional MPWM modulators, the proposed architecture provides significant wider design space such that the efficiency of system can be effectively optimized. A general transmitter architecture based on the proposed concept is analyzed in terms of power efficiency. Efficiency optimization procedures are presented according to input magnitude statistics. Based on the proposed modulator, an optimized 2.4‐GHz RF transmitter is designed in a 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. The circuit‐level simulations show that it delivers 25.8‐dBm peak output power with 46.1% peak efficiency. For a 20‐MHz worldwide interoperability for microwave access (WiMAX) signal with 8.5‐dB peak‐to‐average‐power ratio (PAPR), this transmitter achieves 28.8% (average) efficiency at 17.3‐dBm (average) output power with an error vector magnitude (EVM) of 2.97% rms.     

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

A family of bulk‐driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3‐0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain‐bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18‐μm n‐well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.6 V, 2.11 MHz, 62 dB SFDR active‐RC filter in 0.13µm CMOS process

Active‐RC biquad is proposed, which allows the DC level of the input of operational amplifier (op‐amp) to be different from that of the op‐amp output, enabling the low‐voltage operation. The proposed biquad realizes a second‐order transfer function with only one op‐amp, rendering even lower power consumption. By cascading two biquads, a 0.6 V fourth‐order filter is realized in a 0.13µm CMOS technology. While dissipating only 0.42 mW, the filter shows 2.11 MHz cut‐off frequency and 62 dB spurious‐free dynamic range. Copyright © 2008 John Wiley & Sons, Ltd.     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output‐capacitorless quasi‐digital complementary metal‐oxide‐semiconductor (CMOS) low‐dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade‐off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post‐simulated in HSPICE in a 0.18 µm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on‐chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

67‐90 GHz broadband power detector with 3 GHz output bandwidth for on‐chip test of millimeter‐wave circuits

This paper presents the design of a compact and wide bandwidth millimeter‐wave power detector, integrated at the output of an E‐band power amplifier and implemented in a 55‐nm SiGe BiCMOS process. It is based on a nonlinear PMOS detector core, and its measured output voltage tracks the output power of the PA from 67 to 90 GHz. It provides an insertion loss lower than 0.2 dB, and its responsivity can be tuned between 8 and 17 V/W. The output bandwidth is bigger than 3 GHz, which allows built‐in self‐test when transmitting multigigabit millimeter‐wave signals.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Dimmable integrated CMOS LED driver based on a resonant DC/DC hybrid‐switched capacitor converter

This paper presents a 7.7 ‐ mm² on‐chip LED driver based on a DC/DC resonant hybrid‐switched capacitor converter operating in the MHz range with and without output capacitor. The converter operation allows continuously dimming the LED while keeping control on both peak and average current. Also, it features no flickering even in the absence of output capacitor and for light dimmed down to 10% of the nominal value. The capacitors and switches of the LED driver are integrated on a single IC die fabricated in a low‐cost 5 V 0.18‐μm bulk CMOS technology. This LED driver uses a small (0.7 mm²) inductor of 100 nH, which is 10 times smaller value than prior art integrated inductive LED drivers, still showing a competitive peak efficiency of 93% and achieving a power density of 0.26 W/mm² (0.34 W/mm³).     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.