High‐efficiency CMOS push‐pull power amplifier with multilayer center‐tapped transformer

This paper describes the design of a push‐pull power amplifier (PA) with a center‐tapped transformer for transmitter applications on the 5.2‐GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double‐ended push–pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse‐phased cascode‐connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1‐dB compression point (P1dB), and 27.4% maximum PAE. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

An adaptive digital processor for power efficiency enhancement in hybrid supply modulators

A novel digital envelope modulator for envelope tracking radio frequency power amplifier is presented in this paper. The proposed modulator consists of a parallel combination of linear class AB and switching class D power amplifiers that are controlled digitally. In the previous analog architectures, the requirements needed for the AB operational amplifier such as high‐current driving capability, high bandwidth and large output swing is usually obtainable at high overall static power dissipation. The digitally controlled power opamp presented here not only provides the aforementioned requirements but also reduces power dissipation compared with previous work. Furthermore, the digital control of the modulator makes it adaptive to the input signal variations in comparison with conventional analog parallel hybrid envelope modulators. The digital processor of the modulator is evaluated with a 45‐nm complementary metal oxide semiconductor technology. The overall power consumption of the digital processor is around 142 mW at 1.5‐GHz clock frequency. As an application, the designed digital class AB is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital processor power consumption, is around 82% at an average 32 dBm output power for a 5‐MHz input signal. Copyright © 2015 John Wiley & Sons, Ltd.     

RF transmitter using the dual‐pulse position modulation method for low‐power smart micro‐sensing chip

This paper presents a low‐power radio frequency (RF) transmitter using dual‐pulse position modulation (DPPM) for a smart micro‐sensing chip (SMSC) with sensors and large scale integrated circuit (LSI) on the same chip. The DPPM method is presented by a fixed pulse and a variable pulse within the same time frame. The distance between the fixed pulse and the variable pulse describes the amplitude of the input signal. A modulator and a ring oscillator were designed for the RF transmitter using the DPPM method. In the modulator, the pulse width modulation (PWM) signal is generated by the intersective method, and narrow pulses are extracted at the rising and falling positions of the generated PWM signal. The designed oscillator has the function of an oscillation controller. The RF transmitter was fabricated with sensors for an SMSC by complementary metal–oxide–semiconductor (CMOS) technology. The power consumption of the fabricated modulator was 4.5 mW. The power consumption of the proposed RF transmitter was measured as 7.0–7.3 mW at an input signal of 0.8–2.5 V. The RF transmitter using the DPPM method was able to reduce the power consumption by a maximum of 50.3% compared to a transmitter using the PWM method, because in the latter the dissipated power was 8.4–14.5 mW at the same input signal. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

Optimum design of high power and high efficiency mm‐wave fundamental oscillators

A systematic method to design high power and high efficiency mm‐wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77‐GHz two‐stage (differential) VCO is designed in a 65‐nm CMOS process. Careful electromagnetic and circuit simulations demonstrate that the designed VCO has 2‐GHz tuning range, maximum output power of 10.5 dBm and maximum DC to RF efficiency of 24.1%. The designed VCO shows 54.8% and 108.7% improvement in terms of maximum output power and efficiency compared with a conventional cross‐coupled VCO with the same tuning range.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

High dynamic range pseudo–two-level digital pulse-width modulation for power-efficient RF transmitters

Radio frequency (RF) power amplification based on pulse-width modulation (PWM) has been widely discussed as a potential solution to achieve higher efficiency in RF transmitters. A digitally implemented PWM introduces a large amount of in-band distortion due to spectral aliasing. In this paper, a novel memoryless PWM modulator with a built-in anti-aliasing filter is proposed that effectively reduces the in-band distortion in digital implementation. The spectral characteristics of the proposed PWM modulator as well as the statistical properties of its output PWM signal are analytically studied. The pseudo–two-level output of the proposed modulator provides the capability to compromise between the efficiency, linearity, and complexity of transmitter, based on the given design targets. The proposed PWM method benefits from a simple circuit implementation in both digital and RF sections of the transmitter. Moreover, it preserves the low distortion property at low oversampling ratios of digital baseband. Simulations, as well as measurements, verify the performance of the proposed method.     

Evaluation Results of the Signal Decomposition Technique for OFDM Transmission which Achieves the Power‐Added Efficiency Improvement and the SNR Enhancement Using the Noise Elimination

The authors have proposed the signal decomposition technique as one of the powerful solution to mitigate the large peak‐to‐average power ratio (PAPR) to be addressed in orthogonal frequency division multiplexing (OFDM) transmitters especially on mobile terminals. In order to enhance the receiver SNR, the simple noise elimination techniques working together with the signal decomposition technique have also been proposed that eliminates the noise added on the decomposed constant amplitude on‐off‐signals taking advantage of the knowledge of their constant amplitude at the receiver. In this paper, we discuss the parameter design issue of the proposed techniques and their optimization. Then, demonstrate the PAPR, the power‐added efficiency (PAE), and also the BER performances operating on the optimized parameters. It is confirmed that the proposed signal decomposition technique improves the PAPR by 4 dB and doubles the PAE at the complementary cumulative distribution function of 1%. It is also confirmed that the proposed noise elimination technique improves the receiver SNR by 3 dB at the BER of 10 to 3, which is nearly equal to that of conventional OFDM, under the conditions that the decomposed signals are transmitted over the independent additive white Gaussian noise channels. Furthermore, it is demonstrated that the proposed techniques work properly when the decomposed signals are transmitted over 2 × 2 multi‐input multi‐output.     

A new single‐phase high‐power‐factor converter with buck and buck–boost hybrid operation

In recent years, a wide variety of high‐power‐factor converter schemes have been proposed to solve the harmonic problem. The schemes are based on conventional boost, buck, or buck–boost topology, and their performance, such as output voltage control range in the boost and buck topology or efficiency in the buck–boost topology, is limited. To solve this, the authors propose a single‐phase high‐power‐factor converter with a new topology obtained from a combination of buck and buck–boost topology. The power stage performs the buck and buck–boost operations by a compact single‐stage converter circuit while the simple controller/modulator appropriately controls the alternation of the buck and buck–boost operation and maintains a high‐quality input current during both the buck and buck–boost operations. The proposed scheme results in a high‐performance rectifier with no limitation of output voltage control range and a high efficiency. In this paper, the principle and operation of the proposed converter scheme are described in detail and the theory is confirmed through experimental results obtained from 2‐kW prototype converter. © 2000 Scripta Technica, Electr Eng Jpn, 131(3): 91–100, 2000     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis and design of an active‐clamping zero‐voltage‐switching isolated inverse‐SEPIC converter

This paper presents an active‐clamping zero‐voltage‐switching (ZVS) isolated inverse‐SEPIC converter. The high voltage spikes when turning off the switches are eliminated. The energies stored in the parasitic elements can be recycled to achieve the ZVS of switches. Therefore, the conversion efficiency increases substantially, yet with a reduced circuit cost. Detailed analysis and design of the proposed topology are described. Experimental results are recorded for a prototype converter with a DC input voltage ranging from 130 to 180 V, an output voltage of 12 V and a rated output power of 120 W, operating at a switching frequency of 65 kHz. The average active‐mode efficiency is above 88%. Copyright © 2010 John Wiley & Sons, Ltd.     

Fully integrated 2.45‐GHz OOK receiver for wireless sensor networks

This paper introduces an optimized receiver architecture using the current‐reuse technique to improve receiver sensitivity while minimizing power consumption. An ISM band wireless receiver with OOK modulation was implemented in the TSMC 0.18‐µm CMOS process. The receiver contains an RF front end, an LC‐tank based LO VCO, an IF amplifier and an OOK demodulator. In addition, the IF amplifier features a self‐mixing elimination mechanism which allows the BER to upgrade more than one order of magnitude. Measurement results show a sensitivity of ?63 dBm given a BER of 10^?3. Using the gain‐improving method, the sensitivity is improved by 4 dB (100‐kbps data rate). Including the bias circuit, overall power consumption is less than 383 μW under a 1.2‐V supply, providing an alternate solution for wireless radio applications. Copyright © 2016 John Wiley & Sons, Ltd.     

Prototype Experiments on a 1/32‐Scale Model Via‐Wheel Power Transfer Electric Vehicle

Electric vehicles (EVs) are expected to play a leading role in the changeover from fossil fuels to clean energy. However, EVs are currently not very popular, owing to their short cruising distance and long charging time. Wireless power transfer from the infrastructure to running EVs is expected to be the solution to these problems. Electric vehicle and electrified roadway (EVER) has been proposed as a wireless power transfer system for EVs while in motion. Via‐wheel power transfer (V‐WPT) is expected to be a wireless power transfer scheme for EVER. We designed and prototyped a 1:32 scale model of a V‐WPT system that consists of an RF inverter, an electrified roadway, a rectifier, and an EV with a dc motor. The output power of the prototype RF inverter was 5.9 W and the dc–RF conversion efficiency was 36.6%. The LC matching circuits for the V‐WPT were designed with two‐port conjugate matching because S₁₁ of the V‐WPT was intrinsically –0.06 dB. After matching, the S₁₁ value was reduced to –21.5 dB. The power transmission efficiency of the V‐WPT system was 75%. The RF–dc conversion efficiency of the rectifier was 62%. The total efficiency of the EVER system was 24.2%.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

Dedicated model for the efficient assessment of wireless power transfer in the radiative near‐field

In this paper, a novel method to efficiently calculate the power transfer efficiency of a wireless power transfer system in the radiative near‐field is proposed. The technique allows repositioning of the antennas without large additional cost. It relies on a single simulation (or measurement) of the radiation pattern of the antennas used. Thanks to its high computational efficiency, it can be used in multi‐transmitter and multi‐receiver scenarios when there is no coupling between devices via the reactive near‐field. Our method is applied to the latter to demonstrate its accuracy and computational efficiency. Copyright © 2015 John Wiley & Sons, Ltd.