Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.     

A fast temperature-aware fixed-outline floorplanning framework using convex optimization

With aggressive scaling of CMOS technology, it is essential to consider chip temperature in all design levels of digital systems to improve chip reliability and leakage power consumption. In this paper, we present a two phase fixed-outline floorplanning framework that attempts to reduce the peak-temperature of the chip. The first phase distributes evenly the available dead space between the floorplan blocks of a chip, so as to reduce the peak-temperature. The second phase employs a two-stage convex optimization formulation to perform fixed-outline floorplanning such that minimizes the peak-temperature while satisfying physical constraints. To mitigate the time and computational complexity of capturing the temperature behavior, we present a less computational expensive analogous formulation that approximates the temperature of a block by its corresponding power density. Although, the corresponding power density formulation exhibits lower complexity the experimental results demonstrate its high degree of accuracy. Moreover, this formulation manages to achieve significant improvements in terms of peak-temperature and runtime for almost all of the test cases. We investigate the trade-off between peak-temperature and area as well and provide conditions that result in a reasonable reduction of peak-temperature with minimum increase of the dead space.     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.     

面向软模块的稳定固定边框布图规划算法

该文提出一种稳定的面向软模块的固定边框布图规划算法。该算法基于正则波兰表达式(Normalized Polish Expression, NPE)表示,提出一种基于形状曲线相加和插值技术的计算NPE最优布图的方法,并运用模拟退火(Simulation Annealing, SA)算法搜索最优解。为了求得满足固定边框的布图解,提出一种基于删除后插入(Insertion After Delete, IAD)算子的后布图优化方法。对8个GSRC和MCNC电路的实验结果表明,所提出算法在1%空白面积率的边框约束下的布图成功率接近100%,在总线长上较已有文献有较大改进,且在求解速度上较同类基于SA的算法有较大优势。     

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine

Multi-supply voltage (MSV) technique is one of the efficient ways to reduce power consumption. However, MSV makes the physical design much more complicated. Especially, the randomized algorithm consumes much time as the size of the problem increases and the constraint of rectangular shaped voltage island limits better solutions in terms of power. In this paper, a nonrectangular shaped voltage island (NSVI) aware floorplanning is proposed with nonrandomized searching engine for efficient floorplanning. With a generalized slicing tree, a hypergraph is generated according to the cores' legal voltage levels, which is favorable to cluster cores working under the same voltage level together so that the called NSVIs can be generated easily. The proposed approach can deal with the fixed-outline floorplanning and perform well under different aspect ratios. Experimental results on GSRC benchmark suites indicate that the proposed method can obtain better solutions with less CPU time than published methods.     

Bus-driven floorplanning with thermal consideration

As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.     

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.     

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Three-dimensional (3D) ICs have the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm,which takes use of quadratic uniformity modeling approach. In this model, cell distribution and thermal dissipation are integrated and formulated as a quadratic function through discrete cosine transformation (DCT) with wirelength optimization. Quadratic programming method is utilized to solve the unified quadratic objective function. We update the unified cell distribution and thermal dissipation with each step of the iterative placement process. Thermal distribution was considered enough during placement process even when a cell was moved. To save time, two fast methods to reflect thermal change were proposed for thermal distribution computation. The experimental results show our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wire length.     

固定边框的多电压布图规划算法

多电压设计是应对SoC功耗挑战的一种有效方法,但会带来线长、面积等的开销。为减少线长、芯片的空白面积及提高速度,提出了一种改进的固定边框多电压布图方法.对基于NPE（Normalized Polish Expression）表示的布图解,采用形状曲线相加算法来计算其最优的布图实现,并通过增量计算方法来减少计算NPE及多电压分配的时间.为使所得布图解满足给定的边框约束,提出了一个考虑固定边框约束的目标函数,并采用删除后插入（Insertion after Delete,IAD）算子对SA求得布图解进行后优化.实验结果表明,和已有方法相比,所提出方法在线长和空白面积率方面有较明显优势,且所有电路在不同高宽比、不同电压岛数下均实现了极低的空白面积率（< <1%）.     

Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.     

Floorplanning for low power IC design considering temperature variations

Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.     

Thermal modeling and analysis of 3D multi-processor chips

As 3D chip multi-processors (3D-CMPs) become the main trend in processor development, various thermal management strategies have been recently proposed to optimize system performance while controlling the temperature of the system to stay below a threshold. These thermal-aware policies require the envision of high-level models that capture the complex thermal behavior of (nano)structures that build the 3D stack. Moreover, the floorplanning of the chip strongly determines the thermal profile of the system and a quick exploration of the design space is required to minimize the damage of the thermal effects.This paper proposes a complete thermal model for 3D-CMPs with building nano-structures. The proposed thermal model is then used to characterize the thermal behavior of the Niagara system and expose the strong influence of the chip floorplanning in the thermal profile.     

Multi-scale Single Image Super-Resolution with Remote-Sensing Application Using Transferred Wide Residual Network

In the integrated circuit (IC) designing floorplanning is an important phase in the process of obtaining the layout of the circuit to be designed. The floorplanning determines the performance, size, yield, and reliability of VLSI ICs. The obtained results in this step are necessary for the other consecutive process of the chip designing. VLSI floorplanning from the computational point of view is a non-polynomial hard (NP-hard problem), and hence cannot be efficiently solved by the classical optimization techniques. In this paper, we have proposed a metaheuristic approach to address the problem by using the parallel particle swarm optimization (P-PSO) technique. The P-PSO uses a new greedy operation on the sequence pair (SP) to explore the search space to find an optimal solution. Experimental results on the Microelectronic Centre of North Carolina and Gigascale Systems Research Center benchmark shows that the applied parallel PSO (P-PSO) may be used to produce an optimal solution.

     

Maximising energy efficiency in 3D multicore systems: a formalised approach

Three-dimensional integrated circuits (3D ICs) present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this article, we analyse for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power. We develop a novel convex optimisation framework to optimise the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation-based experiments with our proposed optimisation framework shows 5–17% improvement in the energy efficiency of a typical multicore system organised as 3D stacked dies.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

An exact algorithm for wirelength optimal placements in VLSI design

We present a new algorithm designed to solve floorplanning problems optimally. More precisely, the algorithm finds solutions to rectangle packing problems which globally minimize wirelength and avoid given sets of blocked regions. We present the first optimal floorplans for 3 of the 5 intensely studied MCNC block packing instances and a significantly larger industrial instance with 27 rectangles and thousands of nets. Moreover, we show how to use the algorithm to place larger instances that cannot be solved optimally in reasonable runtime.     

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or ${B}^{ast}$-tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.      

Simulation of electrical overstress thermal failures in integratedcircuits

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (ICs) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM's computational efficiency to handle large-scale EOS thermal problems in ICs derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data     

Three-step pin assignment algorithm for building block layout

A new pin assignment algorithm is proposed which can be used in floorplanning and building block layout to minimise the total wiring length and channel area while satisfying the minimum distance constraint among pin positions on the block boundary. This algorithm can be used in floorplanning in which block shapes are iteratively modified by the channel density obtained as a result of global routing. The proposed pin assignment algorithm occurs in three steps: approximate pin assignment, global routing and detailed pin assignment. Experimental results were obtained using MCNC placement and floorplanning benchmark examples.<>     

低热梯度导向的三维FPGA互连通道网络架构研究

该文针对3维FPGA (3D FPGA)芯片存在的散热问题,提出具有低热梯度特征的互连网络通道结构,力图解决传统FPGA匀称互连通道设计在芯片堆叠实现上产生的温度非平衡现象。该文建立了3D FPGA的热阻网络模型;对不同类型的通道线对3D FPGA的热分布影响进行了理论分析和热仿真;提出了垂直方向通道网络非均匀分布的3D FPGA通道结构,实验表明,与给定传统FPGA互连通道结构相比,采用所提方法实现的3D FPGA设计架构能够降低76.8%的层间最高温度梯度,10.4%的层内温度梯度。